Exercise set
PCB Power Integrity and PDN Design Exercises
Solved PCB power integrity exercises for target impedance, decoupling, via droop, copper loss, thermal margin and PDN release evidence.
These exercises treat PCB power integrity as a release problem for rails, copper, vias, regulators and local energy storage. They focus on target impedance, decoupling placement, package and via inductance, voltage droop, anti-resonance, copper temperature, regulator margin and evidence needed before a board is released.
Use the numbers as first-pass engineering checks. A production board still needs stackup data, component tolerances, capacitor bias derating, regulator loop stability, fabrication notes, thermal measurement and a test record tied to the exact board revision.
Release Evidence Notes
Power-integrity calculations are useful only when they point to physical evidence. Record the board revision, rail name, load state, firmware mode, measurement bandwidth, probe geometry, stackup, copper weight, component population and acceptance threshold. If any of those items changes, repeat the relevant checks.
Engineering Boundary Notes
The models below use lumped impedance, first-order thermal resistance and simplified parasitics. They do not replace field-solver impedance, package models, VRM loop analysis, spreading resistance, capacitor vendor data, DC bias derating or lab correlation. Use them to reject weak designs early and to define what must be measured.
Common Release Mistakes
- using nominal capacitance without DC bias, tolerance and aging derating;
- checking a target impedance at one frequency while the load current excites another band;
- accepting a rail because the regulator output is stable while the load pins see droop;
- ignoring shared via inductance and return-current crowding;
- treating copper temperature rise as independent from enclosure airflow;
- measuring ripple with a long probe ground lead and approving a false waveform.
Scenario Map
The exercises progress from rail budget and target impedance to capacitor choice, via and copper limits, local droop, anti-resonance, thermal release and board-level evidence. They are written for digital, mixed-signal and power-control boards where a rail must survive fast load current and real layout parasitics.
Exercise 1: Rail Tolerance Budget
A 1.0 V core rail allows a total deviation of 5 percent. The DC regulator accuracy is 1.5 percent and the static IR drop allowance is 12 mV. How much transient droop remains available?
Solution
The total allowed deviation is
The regulator tolerance consumes 15 mV, so the remaining transient budget is
Engineering Comment
The rail is not allowed to spend the same voltage budget three times. DC tolerance, copper loss and dynamic droop all subtract from the same limit at the load pins.
Plausibility Check
Twenty-three millivolts is 2.3 percent of a 1.0 V rail, a realistic but tight digital-core droop target.
Exercise 2: Target Impedance from Load Step
A processor load can step by 6 A. The allowed transient droop from the budget is 24 mV. Estimate the maximum target impedance.
Solution
The PDN should stay below about 4 mOhm over the relevant current-spectrum band.
Engineering Comment
Target impedance is a specification for the whole path seen by the load: regulator output, planes, vias, package, capacitors and mounting inductance.
Plausibility Check
A few milliohms is typical for high-current low-voltage rails; a single capacitor cannot satisfy this over the full band.
Exercise 3: Bulk Capacitance for a Slow Load Step
A 3 A load step lasts 8 us before the regulator loop can restore charge. Limit droop to 30 mV. Estimate the ideal bulk capacitance before derating.
Solution
The ideal value is 800 uF before ESR, ESL, tolerance and bias derating.
Engineering Comment
Bulk capacitance covers slower energy deficits. Ceramic capacitors near the load are still needed for faster edges where inductance dominates.
Plausibility Check
Hundreds of microfarads are plausible for a multi-amp rail with microsecond-scale regulator response.
Exercise 4: Effective Capacitance after Derating
Four 47 uF ceramic capacitors retain 45 percent of their nominal value under DC bias and temperature. What is the effective capacitance?
Solution
Engineering Comment
High-K ceramics can lose most of their nominal capacitance under bias. A BOM value without voltage, dielectric, package and bias curve is weak release evidence.
Plausibility Check
Losing more than half the nominal value is common for small high-density MLCCs on low-voltage rails.
Exercise 5: Decoupling Resonant Frequency
A 22 uF capacitor has 0.7 nH mounting inductance. Estimate its series resonant frequency.
Solution
Engineering Comment
Below resonance the capacitor behaves capacitively; above resonance the mounting inductance dominates. Placement and via geometry can matter as much as nominal capacitance.
Plausibility Check
A microfarad-range MLCC mounted with sub-nH inductance resonating in the low MHz range is reasonable.
Exercise 6: Via Inductance Droop
A power via path has 1.2 nH total inductance. A device draws a 2 A current step in 1 ns. Estimate the inductive voltage spike.
Solution
Engineering Comment
This first-order number is intentionally alarming: very fast current edges cannot be supplied through a long inductive path. Local capacitance and low-inductance mounting are mandatory.
Plausibility Check
The spike exceeds the rail voltage, which means the assumed current edge cannot be supported by that path alone.
Exercise 7: Parallel Via Reduction
Six identical power vias each contribute 0.9 nH when used in parallel. Estimate the ideal equivalent inductance.
Solution
Engineering Comment
Parallel vias reduce inductance only when current shares well and the return path is equally compact. Spreading, pad geometry and plane transitions limit the ideal improvement.
Plausibility Check
The result is lower than a single via but not zero; sub-nH mounting is the point of dense via stitching.
Exercise 8: DC Copper Voltage Drop
A rail trace has 8 mOhm resistance at operating temperature and carries 4 A. Compute DC voltage drop and power loss.
Solution
Engineering Comment
Thirty-two millivolts may consume a large share of a low-voltage rail budget. Copper width, plane pours and remote sensing are not cosmetic choices.
Plausibility Check
A tenth of a watt in board copper is measurable but not extreme; it still matters near dense components.
Exercise 9: Plane Resistance from Sheet Resistance
A rectangular copper region has sheet resistance 0.5 mOhm per square and geometry of 6 squares. What is its resistance?
Solution
Engineering Comment
Sheet resistance is useful for quick plane estimates, but current crowding around vias and neck-downs can make the real local resistance higher.
Plausibility Check
Milliohm values are plausible for short copper planes; narrow thermal spokes or bottlenecks would change the answer.
Exercise 10: Copper Temperature Rise Power Screen
A copper neck dissipates 0.42 W. A conservative board-level thermal resistance estimate for that region is 55 K/W. Estimate temperature rise.
Solution
Engineering Comment
Power integrity and thermal integrity are coupled. Hot copper has higher resistance, which increases drop and can further heat the region.
Plausibility Check
A rise of about 23 C is believable for a localized bottleneck; it should trigger layout review if ambient is high.
Exercise 11: Junction Temperature from Board Temperature
A regulator dissipates 1.1 W. Its junction-to-board thermal resistance is 18 K/W and measured board temperature near the package is 64 C. Estimate junction temperature.
Solution
Engineering Comment
For release, this estimate must be compared with component rating, derating policy and the actual enclosure airflow or still-air condition.
Plausibility Check
An 84 C junction is plausible and may be acceptable for many ICs, but derating could still reject it.
Exercise 12: Regulator Current Margin
A rail has a measured steady load of 3.8 A, a worst-case transient addition of 1.1 A and a regulator current limit of 6.0 A. What is the margin?
Solution
The current-limit margin is about 22 percent.
Engineering Comment
Current limit is not an operating setpoint. It varies with temperature, part tolerance and foldback behavior, so release usually needs more than a nominal 22 percent margin.
Plausibility Check
The rail is below the limit, but close enough that inrush, tolerance and thermal derating must be checked.
Exercise 13: Inrush Charge
A rail has 940 uF effective capacitance and ramps from 0 V to 5 V in 3 ms. Estimate average capacitor charging current.
Solution
Engineering Comment
The regulator, upstream fuse, connector and sequencing controller must tolerate inrush in addition to normal load current.
Plausibility Check
An ampere-scale inrush for nearly one millifarad on a 5 V rail is expected.
Exercise 14: Capacitor Ripple Current Sharing
Three identical bulk capacitors share 2.4 A rms ripple current equally. Each is rated for 1.1 A rms at the board temperature. Is the rating acceptable?
Solution
Each capacitor has
or 37.5 percent current margin.
Engineering Comment
Equal sharing is an assumption. ESR tolerance, placement and heating can unbalance ripple current, so measurement or conservative derating is needed.
Plausibility Check
The nominal result passes, but the release decision should not depend on perfect current sharing.
Exercise 15: Anti-Resonance Peak Screen
A PDN impedance scan shows a 38 mOhm anti-resonance peak at 18 MHz. The target impedance is 12 mOhm. What is the excess ratio?
Solution
The peak is about 3.2 times the target.
Engineering Comment
Anti-resonance can occur when capacitor groups interact. Adding more capacitance without damping may sharpen the peak instead of improving release behavior.
Plausibility Check
A factor above 3 is too large to ignore; the board needs damping, capacitor selection changes or load-spectrum justification.
Exercise 16: Load-Step Measurement Bandwidth
A load step has a 2 ns edge. Estimate the minimum oscilloscope bandwidth for a first-pass measurement using the 0.35 rise-time rule.
Solution
Engineering Comment
Bandwidth is necessary but not sufficient. Probe inductance, loop area, fixture loading and ground connection can dominate the observed ripple.
Plausibility Check
Hundreds of MHz for nanosecond rail events is realistic.
Exercise 17: Remote-Sense Error
A regulator senses voltage at its output pins while the load is 35 mV lower because of copper and connector drop. If the rail specification allows 50 mV total deviation, what fraction is consumed before transient droop?
Solution
Seventy percent of the deviation budget is consumed by static distribution loss.
Engineering Comment
Remote sensing or wider copper may be required. Otherwise the transient budget becomes unrealistically small.
Plausibility Check
Consuming most of the tolerance in static drop is a common failure mode on low-voltage high-current rails.
Exercise 18: PDN Release Gate
A release checklist has 14 required power-integrity evidence items. Eleven are complete, two are incomplete and one is not applicable with documented justification. What is the completion fraction for applicable items?
Solution
Applicable items are
The completion fraction is
or about 84.6 percent. The release gate is not complete.
Engineering Comment
Power integrity release is a configuration decision. Missing evidence on the exact board revision should block release even if calculations look favorable.
Plausibility Check
Two missing applicable items are not a rounding error; they are unresolved release risk.
Validation Package Checklist
Before accepting a PCB power-integrity release, collect:
- rail voltage budgets from regulator tolerance through load-pin transient droop;
- target-impedance calculations tied to load-current spectra;
- effective capacitance after bias, tolerance, aging and temperature derating;
- via, plane, copper-neck and connector drop estimates;
- anti-resonance scans or justified frequency-band exclusions;
- load-step measurements with probe geometry and bandwidth stated;
- regulator current, inrush, thermal and sequencing evidence;
- board revision, stackup, BOM, firmware state and acceptance limits in the release record.