Power Electronics and Converter Systems Formula Sheet

This formula sheet collects first-pass calculations for power electronics and converter systems. Use it to screen DC links, rectifiers, DC-DC converters, inverters, semiconductor stress, switching loss, thermal limits, filters, protection timing, stored energy, leakage current, and validation margins.

The equations are not a substitute for a device data sheet, electromagnetic compatibility test, protection study, thermal model, layout review, or control-loop validation. They are useful when the converter boundary, operating case, RMS and peak quantities, temperature limits, switching frequency, source impedance, load profile, and fault response are clearly stated.

Boundary and Sign Convention

Define the boundary before calculating power or efficiency:

Efficiency:

Loss:

For bidirectional converters, define signs explicitly. A common convention is:

• P>0 when power flows from the DC source to the load or grid;
• P<0 when power returns to the DC source, battery, brake chopper, or grid;
• voltages and currents are RMS for AC quantities unless marked as peak or instantaneous.

Use separate cases for continuous operation, overload, startup, regeneration, weak source, short circuit, maintenance, and firmware update. A converter can pass one case and fail another.

DC-Link Energy and Hold-Up

Capacitor energy:

Energy available between two DC-link voltages:

Required capacitance for hold-up:

where:

• P is load power during the interruption;
• \Delta t is ride-through time;
• V_1 is initial DC-link voltage;
• V_2 is minimum acceptable DC-link voltage.

This equation assumes constant load power and ignores converter efficiency during the event. Include efficiency if the load boundary is downstream of another conversion stage.

Worked Hold-Up Example

A 60\ \text{kW} converter must ride through:

The DC link can fall from:

to:

Required energy:

Required capacitance:

So:

Engineering interpretation: this is an ideal energy screen. A real design must also check capacitor ripple current, precharge, discharge time, fault energy, voltage balance, lifetime, volume, cost, and the actual load behavior during ride-through.

DC-Link Ripple and Rectifier Screens

For a capacitor-fed DC link with approximately constant current draw:

where f_r is ripple frequency. For a full-wave single-phase rectifier:

For a six-pulse three-phase rectifier:

Ideal average DC voltage for a three-phase diode bridge with continuous current:

For a single-phase bridge with a large capacitor and light ripple:

where V_D is diode forward drop. These are screening equations. Real rectifier voltage depends on source impedance, conduction angle, load current, diode drops, transformer regulation, harmonics, and DC-link ripple.

Buck Converter

Ideal continuous-conduction duty cycle:

Inductor ripple current:

Inductance from target ripple:

Inductor peak current:

Output capacitor ripple screen:

ESR ripple:

Use the worst case for each stress. Maximum ripple may occur at a different input voltage than maximum current, thermal stress, or transient duty.

Worked Buck Inductor Example

A buck converter has:

Switching frequency:

Target inductor ripple is 30\% of output current:

Ideal duty cycle:

Required inductance:

So:

Peak current:

Engineering interpretation: the selected inductor must be checked against saturation current at temperature, RMS current rating, copper loss, core loss, tolerance, and transient current limit. Selecting from 8\ \text{A} average current alone is not enough.

Boost and Buck-Boost Converters

Ideal boost duty cycle:

Boost input inductor average current:

Boost inductor ripple:

Ideal inverting buck-boost voltage magnitude:

Boost converters often fail at low input voltage because input current rises as V_{in} falls:

Check inductor peak current, switch current, diode or synchronous rectifier current, thermal stress, and current-limit margin at minimum input voltage and maximum load.

Flyback Converter

Magnetizing energy per switching cycle:

Approximate output power:

Peak current from power:

Reflected voltage:

Approximate primary switch voltage stress:

Flyback formulas are highly topology-dependent. Leakage inductance, snubber design, transformer construction, clamp voltage, diode recovery, insulation, and thermal behavior can dominate the real design.

Three-Phase Inverter Output

For a two-level three-phase inverter with sinusoidal PWM in the linear modulation region:

Fundamental line-to-line RMS voltage:

Numerically:

where m_a is modulation index. Three-phase apparent power:

Real power:

If motor efficiency is included:

Worked Inverter Output Example

An inverter has:

Fundamental line-to-line RMS voltage:

If line current is:

then apparent power is:

So:

At power factor:

real electrical power is:

Engineering interpretation: the voltage screen assumes linear modulation and ignores voltage drops, dead time, overmodulation, common-mode effects, cable voltage stress, motor back EMF, and current-control limits. The installed system must be validated at the actual cable length, switching frequency, motor, grounding method, and control settings.

Semiconductor Conduction and Switching Loss

MOSFET conduction loss:

Diode conduction loss:

IGBT conduction screen:

Switching loss from energy data:

Approximate hard-switching loss:

Gate-drive loss:

Total device loss screen:

where P_{rr} is reverse-recovery-related loss and P_{aux} includes driver, bootstrap, snubber, or clamp losses when relevant.

Use data at temperature. R_{DS(on)}, diode drop, switching energy, reverse recovery, threshold behavior, and safe operating area vary with junction temperature, current, voltage, gate resistance, layout, and switching speed.

Junction Temperature and Thermal Margin

Steady-state junction temperature:

For an assembled path:

Temperature margin:

Relative margin:

For pulsed operation, use transient thermal impedance:

Worked Thermal Example

A switch dissipates:

Ambient temperature is:

Thermal resistances are:

Total thermal resistance:

Junction temperature:

If the limit is:

margin is:

Engineering interpretation: this passes a steady-state screen, but only if the thermal resistances are valid for the actual mounting, airflow, heat sink orientation, interface material, enclosure temperature, and neighboring heat sources. Pulsed overload requires transient thermal impedance, not only steady-state resistance.

Inductors, Capacitors, and Ripple Stress

Inductor stored energy:

Inductor copper loss:

Inductor saturation margin:

Capacitor RMS heating:

Capacitor voltage margin:

Capacitor lifetime often changes strongly with temperature. Use the manufacturer lifetime model rather than a generic rule when the release depends on field life.

Filters, Resonance, and Harmonics

LC resonance:

Capacitive reactance magnitude:

Inductive reactance:

Total harmonic distortion:

where X_n can be voltage or current harmonic RMS magnitude, provided the same quantity is used throughout.

Do not place an undamped filter resonance near a switching-frequency sideband, grid harmonic, motor electrical frequency, or control-loop crossover without analysis. Filter behavior depends on source impedance, load impedance, damping, tolerances, temperature, and layout parasitics.

Fault Energy, Precharge, and Discharge

Capacitive inrush current screen:

Initial precharge current through a resistor:

Precharge time for a simple RC circuit:

Discharge through a resistor:

Time to reach a safe voltage:

Capacitor stored energy before discharge:

Protection energy screen:

For approximately constant fault current:

where I_f is fault current and t_c is clearing time.

Worked Discharge Example

A DC link has:

Initial voltage:

The safe service voltage is:

The discharge resistor is:

Time to safe voltage:

Initial stored energy:

Engineering interpretation: the voltage reaches the stated service threshold in about one minute, but the resistor and enclosure must be rated for the energy and temperature rise. The design also needs a verified indicator or measurement procedure; assuming the link is discharged because the converter is off is not acceptable.

Leakage Current and Common-Mode Capacitance

For a sinusoidal voltage across capacitance:

For a fast switching edge, displacement current can be screened by:

Common-mode leakage increases with parasitic capacitance, switching speed, cable length, motor winding capacitance, filter capacitors, and grounding arrangement. The result can affect residual-current devices, medical leakage limits, electromagnetic interference, bearing currents, and touch current.

Control and Bandwidth Screens

A switching converter should keep control bandwidth well below the switching frequency:

A common first screen is:

This is not a stability proof. Final validation needs loop-gain measurement or a validated model, gain margin, phase margin, load-step tests, line-step tests, saturation behavior, current-limit behavior, digital delay, sampling effects, and anti-windup review.

For a digital controller with sampling period T_s:

Measurement, computation, PWM update delay, and filtering all reduce usable control bandwidth.

Validation Margins

Absolute margin:

Relative margin:

For a lower-bound requirement:

Use margins for voltage, current, temperature, stored energy, fault clearing, insulation, leakage, ripple, harmonic distortion, communication latency, and control stability. A margin is meaningful only when the case, tolerance, measurement uncertainty, and acceptance criterion are defined.

Common Application Errors

Common mistakes include:

1. mixing RMS, peak, average, and peak-to-peak quantities;
2. selecting inductors from average current instead of peak and saturation current;
3. using nominal input voltage when minimum input creates maximum current;
4. ignoring capacitor ripple current and lifetime;
5. treating thermal resistance as valid for a different heat sink, airflow, or enclosure;
6. using ideal duty-cycle equations without checking voltage drops, dead time, current limit, and control range;
7. designing precharge and discharge from voltage only while ignoring stored energy;
8. validating one nominal load point instead of startup, overload, regeneration, weak source, and fault cases;
9. adding filters without checking resonance, damping, and control interaction;
10. assuming firmware protection is fast enough without hardware fault-energy limits.

Minimum Release Evidence

A converter design review should include:

1. operating-case table with voltage, current, power, temperature, and duty cycle;
2. DC-link energy, ripple, precharge, discharge, and stored-energy checks;
3. semiconductor loss, safe-operating-area, and junction-temperature evidence;
4. magnetics saturation, RMS current, core loss, and temperature evidence;
5. capacitor ripple-current, voltage derating, and lifetime evidence;
6. filter resonance, harmonic, leakage-current, and electromagnetic compatibility evidence;
7. protection timing, fault energy, interlock, and safe-state evidence;
8. control-loop stability, current-limit, startup, regeneration, and ride-through tests;
9. measured validation data under the worst credible source, load, cooling, and installation conditions.

Power-electronics formulas are useful only when tied to a named converter boundary and a realistic operating case. The calculation should lead to a design decision: derate, resize, protect faster, cool better, filter differently, change firmware limits, or refuse release until the missing evidence exists.