Exercise set

PCB Signal Integrity, Return Path, and EMC Exercises

Solved PCB signal integrity exercises for delay, skew, termination, return paths, crosstalk, probing, EMC loops and release evidence.

Branch: Electronic Engineering
Content: Exercise set
Updated: Jul 03, 2026
Revision: v1.0.0 · reviewed

These exercises treat PCB signal integrity as a physical routing, return-current and evidence problem. They cover propagation delay, length matching, controlled impedance, termination, via stubs, return-path discontinuities, crosstalk, probing error, common-mode conversion, loop area, EMI screening and release documentation.

Use the calculations as engineering screens. Final approval still needs a real stackup, dielectric data, fabrication tolerance, component models, connector and package effects, lab measurement setup and a release record tied to the board revision.

Release Evidence Notes

Signal-integrity evidence should name the interface, net class, stackup, dielectric material, controlled-impedance rule, reference plane, receiver threshold, timing budget, measurement fixture, probe setup and firmware traffic state. A waveform without those details is not strong release evidence.

Engineering Boundary Notes

The models below use first-order transmission-line, timing and coupling estimates. They do not replace a field solver, IBIS or SPICE model, compliance test, TDR coupon or EMC chamber result. They help decide which routes need detailed analysis and which release claims need measurement.

Common Release Mistakes

routing a fast trace over a plane split and treating the schematic ground symbol as a return path;
matching lengths while ignoring package delay, via delay and connector skew;
selecting a termination value without source impedance and receiver threshold context;
measuring a fast edge with a long ground lead and accepting a probe artifact;
checking only differential skew while ignoring common-mode conversion and mode balance;
declaring EMC readiness from quiet bench operation without loop-area and cable-current review.

Scenario Map

The exercises move from edge-rate screening to delay, skew, termination, via stubs, crosstalk, return-current loops, probing, EMI estimates and release gates. They are written for mixed-signal, embedded and digital boards where layout parasitics change the behavior of the circuit.

Exercise 1: Transmission-Line Screening

A digital output has a 10 percent to 90 percent rise time of 800 ps. A PCB trace is 75 mm long and propagates at 160 mm/ns. Should the trace be treated as electrically long using the one-sixth rise-time rule?

Solution

The one-way delay is

t_d=\dfrac{75}{160}=0.469\ \mathrm{ns}

The screening limit is

\dfrac{t_r}{6}=\dfrac{0.8}{6}=0.133\ \mathrm{ns}

Because 0.469 ns is greater than 0.133 ns, the trace should be treated as a transmission line.

Engineering Comment

Trace length must be judged against edge rate, not clock rate. A slow protocol can still have fast edges that excite reflections.

Plausibility Check

A 75 mm board trace with sub-ns edges is clearly in controlled-routing territory.

Exercise 2: Trace Delay from Length

A source-synchronous data route is 118 mm long. The propagation velocity is 150 mm/ns. Estimate delay.

Solution

t_d=\dfrac{\ell}{v}=\dfrac{118}{150}=0.787\ \mathrm{ns}

Engineering Comment

Delay is a routing attribute. If the timing budget is tight, the board route must be included with device output delay, package skew and receiver setup/hold margins.

Plausibility Check

About 0.8 ns for a 12 cm trace is realistic on FR-4 class material.

Exercise 3: Length Match from Timing Skew

A bus allows 60 ps of board skew. Propagation velocity is 155 mm/ns. What maximum length mismatch is allowed?

Solution

\Delta \ell=v\Delta t=(155\ \mathrm{mm/ns})(0.060\ \mathrm{ns})=9.3\ \mathrm{mm}

Engineering Comment

This is only the board contribution. Package skew, connector skew and receiver sampling uncertainty may reduce the allowed route mismatch.

Plausibility Check

Single-digit millimetre matching is common for moderate-speed source-synchronous buses.

Exercise 4: Differential Pair Skew

The positive side of a differential pair is 4.5 mm longer than the negative side. Velocity is 160 mm/ns. Compute intra-pair skew.

Solution

\Delta t=\dfrac{4.5}{160}=0.0281\ \mathrm{ns}=28.1\ \mathrm{ps}

Engineering Comment

Differential skew converts part of the signal into common mode and can reduce eye margin, especially at connectors or mode-sensitive receivers.

Plausibility Check

Tens of picoseconds from a few millimetres of mismatch is plausible.

Exercise 5: Source Termination Value

A driver has 18 Ohm output resistance and drives a 50 Ohm trace. Estimate the series resistor needed for source termination.

Solution

R_s=Z_0-R_\mathrm{driver}=50-18=32\ \Omega

Engineering Comment

The value should be placed close to the driver and checked against receiver threshold, edge-rate needs and driver current capability.

Plausibility Check

A 33 Ohm standard resistor is a common practical selection.

Exercise 6: Reflection Coefficient at Load

A 50 Ohm trace drives a high-impedance input approximated as 500 Ohm. Estimate the load reflection coefficient.

Solution

\Gamma_L=\dfrac{Z_L-Z_0}{Z_L+Z_0} =\dfrac{500-50}{500+50}=0.818

Engineering Comment

A high-impedance receiver reflects most of the incident wave unless source termination or another damping method controls the round trip.

Plausibility Check

A coefficient close to +1 is expected for a nearly open load.

Exercise 7: RC Edge-Rate Filtering

A 33 Ohm source resistor drives an estimated 6 pF input and trace capacitance. Estimate the 10 percent to 90 percent rise-time contribution using $t_r\approx2.2RC$ .

Solution

t_r\approx2.2RC=2.2(33)(6\times10^{-12}) =4.36\times10^{-10}\ \mathrm{s}

The added rise-time contribution is about 436 ps.

Engineering Comment

Slowing an edge can reduce ringing and EMI, but too much filtering can violate receiver timing or eye-height requirements.

Plausibility Check

Hundreds of picoseconds for tens of ohms and a few picofarads is reasonable.

Exercise 8: Via Stub Resonance

A through-via leaves a 2.8 mm open stub in material with propagation velocity 150 mm/ns. Estimate the quarter-wave resonance frequency.

Solution

f\approx\dfrac{v}{4\ell} =\dfrac{150\ \mathrm{mm/ns}}{4(2.8\ \mathrm{mm})} =13.4\ \mathrm{GHz}

Engineering Comment

If significant spectral energy or compliance margin extends near this frequency, backdrilling or routing changes may be justified.

Plausibility Check

Millimetre-scale stubs resonating in the GHz range is consistent with high-speed PCB behavior.

Exercise 9: Probe Ground Lead Error

A probe ground lead adds 12 nH. The measured edge current change is 0.4 A in 1.5 ns. Estimate the induced error voltage.

Solution

V=L\dfrac{\Delta I}{\Delta t} =(12\times10^{-9})\dfrac{0.4}{1.5\times10^{-9}} =3.2\ \mathrm{V}

Engineering Comment

Long ground leads can create a waveform that is mostly measurement artifact. Use a short spring ground, coax pickoff or differential measurement where appropriate.

Plausibility Check

The error is larger than many logic amplitudes, so the setup is unacceptable for fast-edge validation.

Exercise 10: Crosstalk Noise Margin

A victim net has 450 mV noise margin. Near-end crosstalk is estimated at 95 mV. What fraction of the noise margin is consumed?

Solution

\mathrm{fraction}=\dfrac{95}{450}=0.211

About 21 percent of the margin is consumed.

Engineering Comment

The board may pass this single estimate, but simultaneous aggressors, termination state and receiver threshold variation can raise the actual risk.

Plausibility Check

Consuming one-fifth of the margin is not negligible but is often manageable with spacing or reference-plane improvements.

Exercise 11: Coupled-Length Reduction

A crosstalk estimate is proportional to coupled length. If spacing changes reduce the coupled length from 42 mm to 18 mm, what is the new noise estimate from an original 110 mV?

Solution

V_\mathrm{new}=110\dfrac{18}{42}=47.1\ \mathrm{mV}

Engineering Comment

Short parallel runs, solid reference planes and orthogonal layer transitions are practical layout controls before more complex simulation is required.

Plausibility Check

The reduction is a little more than half, matching the coupled-length reduction.

Exercise 12: Return-Path Detour Loop Area

A trace crosses a plane gap that forces return current to detour 20 mm away for a 35 mm run. Estimate the added loop area.

Solution

A\approx(20\ \mathrm{mm})(35\ \mathrm{mm})=700\ \mathrm{mm^2}

Engineering Comment

Return current follows the path of lowest impedance, not the path of the schematic line. A gap can create a large radiating loop and common-mode noise.

Plausibility Check

Seven hundred square millimetres is large for a high-speed return-current loop on a PCB.

Exercise 13: Magnetic-Field Coupling Screen

A loop area is reduced from 520 mm2 to 130 mm2. If induced noise is proportional to loop area, what is the reduction in dB?

Solution

The voltage ratio is

\dfrac{130}{520}=0.25

The reduction is

20\log_{10}(0.25)=-12.0\ \mathrm{dB}

Engineering Comment

Loop-area reduction is one of the most reliable EMC improvements because it lowers both susceptibility and radiation mechanisms.

Plausibility Check

A four-to-one area reduction corresponds to about 12 dB, which is a meaningful EMC improvement.

Exercise 14: Common-Mode Voltage from Imbalance

A differential signal has 900 mV differential amplitude. Layout imbalance converts 3 percent into common mode. Estimate common-mode amplitude.

Solution

V_\mathrm{CM}=0.03(900\ \mathrm{mV})=27\ \mathrm{mV}

Engineering Comment

Small imbalance can become a cable-radiation or connector-emission problem because common-mode current couples efficiently to external structures.

Plausibility Check

Tens of millivolts of common mode from a nearly 1 V differential signal is credible.

Exercise 15: Source-Synchronous Setup Margin

A clock-to-data budget allows 1.2 ns. Device uncertainty consumes 0.55 ns, receiver setup consumes 0.32 ns and board skew is 0.21 ns. What margin remains?

Solution

t_\mathrm{margin}=1.2-0.55-0.32-0.21=0.12\ \mathrm{ns}

The remaining setup margin is 120 ps.

Engineering Comment

This is a small margin. The board rule should include fabrication tolerance, package mismatch and measurement uncertainty before release.

Plausibility Check

Hundreds of picoseconds matter in source-synchronous timing; 120 ps is not a relaxed design.

Exercise 16: Jitter Budget Consumption

An interface allows 180 ps rms total timing uncertainty. Random jitter is 85 ps rms and deterministic jitter is treated as an equivalent 60 ps rms contribution. Estimate remaining rms margin by root-sum-square subtraction.

Solution

t_\mathrm{used}=\sqrt{85^2+60^2}=104\ \mathrm{ps}

t_\mathrm{remaining}=\sqrt{180^2-104^2}=147\ \mathrm{ps}

Engineering Comment

Jitter accounting must state whether values are peak, rms or bounded deterministic terms. Mixing definitions can create false margin.

Plausibility Check

The remaining rms margin is lower than the total allowance but still substantial because RSS terms do not add linearly.

Exercise 17: EMI Frequency from Edge Rate

A logic edge has 1.0 ns rise time. Estimate the knee frequency using $f_k\approx0.35/t_r$ .

Solution

f_k\approx\dfrac{0.35}{1.0\times10^{-9}} =350\ \mathrm{MHz}

Engineering Comment

EMC review should cover harmonics and resonant structures around the edge-rate band, not only the clock fundamental.

Plausibility Check

A 1 ns edge carrying energy into hundreds of MHz is expected.

Exercise 18: SI Release Gate

A signal-integrity release package requires 16 applicable evidence items. Controlled-impedance data, timing budget, return-path review and crosstalk screen are complete, but eye measurement and EMC pre-scan are missing. If 14 items are complete, what completion fraction remains, and should release pass?

Solution

\mathrm{completion}=\dfrac{14}{16}=0.875

The package is 87.5 percent complete. It should not pass if the missing items are required gates.

Engineering Comment

Release evidence is not a popularity vote. Missing eye or EMC evidence can block the product even when most checklist items are complete.

Plausibility Check

Two missing items out of sixteen is visible risk, especially when they are validation measurements rather than documentation details.

Validation Package Checklist

Before accepting a PCB signal-integrity and EMC release, collect:

stackup, dielectric, copper and controlled-impedance basis;
edge-rate screening for each critical net class;
delay, skew, package and connector timing budgets;
termination assumptions and measured or simulated receiver margins;
return-path continuity review across layer changes, gaps and connectors;
crosstalk, via-stub and common-mode conversion screens;
measurement setup with probe type, bandwidth, fixture and traffic pattern;
EMC loop-area review, cable-current risk and pre-scan or compliance evidence.

REF