Exercise set

Electronic Devices and Analog Circuits Exercises

Solved analog electronics exercises for dividers, diode clamps, zener references, op-amps, RC filters, noise, tolerance, thermal limits and validation.

Branch: Electronic Engineering
Content: Exercise set
Updated: Jul 03, 2026
Revision: v1.0.1 · published

These exercises practise first-pass electronic-device and analog-circuit calculations. They are meant for design review, lab preparation and sanity checks before simulation or board release.

The calculations are intentionally simple enough to do by hand, but each one includes the engineering decision that makes the result useful. A divider can be numerically correct and still load the source. A diode clamp can conduct the expected current and still exceed pulse energy. An op-amp can have the right ideal gain and still fail output swing, bandwidth, slew-rate or bias-current limits.

How to use these exercises

For each problem, compute the requested value and then decide whether the circuit is acceptable for the stated condition. Keep track of whether a value is nominal, worst-case, RMS, peak, DC, small-signal, large-signal or measured.

The formulas here are first-pass checks. Real release also requires datasheets, tolerance analysis, thermal review, layout review, electromagnetic compatibility review, prototype measurement, production test limits and field-failure feedback.

Release Evidence Notes

Analog circuit release evidence should connect the calculation to the actual component, bias point, tolerance, temperature, load, supply range, package, PCB layout and measurement method. A correct nominal answer does not prove that the circuit works across process spread, input range, output swing, noise, bandwidth and thermal limits.

Useful evidence includes schematic revision, component values and tolerances, datasheet operating region, worst-case current, power dissipation, junction temperature, small-signal and large-signal limits, noise basis, source and load impedance, prototype measurements, simulation model assumptions and the production test limit that will detect a failure.

Engineering Boundary Notes

These exercises use compact hand calculations. They do not replace SPICE validation, worst-case tolerance analysis, stability review, electromagnetic compatibility testing, PCB parasitic review, component derating or production-test validation. Device behavior can change when temperature, package, input common-mode range, output swing, frequency or layout parasitics move outside the simple model.

Common Release Mistakes

accepting an ideal op-amp gain while output swing, input range or slew rate fails;
using nominal resistor values while tolerance shifts a threshold or reference;
ignoring diode, zener and transistor power dissipation during pulses;
quoting filter cutoff without source/load impedance and component tolerance;
treating simulation as release evidence without prototype measurement;
validating one supply and temperature while the product spec requires a wider envelope.

Scenario Map

Scenario	Main calculation	Engineering decision
Divider and bias network	loaded divider voltage, Thevenin resistance	Decide whether the load has invalidated the nominal ratio.
Diode and zener circuits	current, power and clamp margin	Check stress before treating a protection part as ideal.
Op-amp stages	gain, swing, bandwidth, slew rate and bias error	Verify real amplifier limits, not only ideal gain.
RC networks	cutoff, attenuation and settling time	Match bandwidth to signal and sampling requirements.
Noise and tolerance	thermal noise, SNR, worst-case and RSS errors	Decide whether the analog front end has enough measurement margin.
Thermal and release gates	junction temperature, derating and evidence	Hold release when one required limit or validation item fails.

Validation Package Checklist

schematic revision, component values and tolerance basis are controlled;
datasheet operating region and derating are checked;
supply, load, temperature and signal envelope match intended use;
bandwidth, noise, slew rate and stability assumptions are stated;
power dissipation and junction temperature are bounded;
prototype measurement and production test limit are identified;
final release action names accept, derate, retest, change component or redesign.

Exercise 1: Loaded voltage divider and Thevenin resistance

A divider uses:

V_{in}=12\ \text{V},\qquad R_1=18\ \text{k}\Omega,\qquad R_2=6.8\ \text{k}\Omega.

The output is loaded by:

R_L=20\ \text{k}\Omega.

Find the unloaded output voltage, loaded output voltage and Thevenin resistance of the divider.

Solution

The unloaded output is:

\displaystyle V_{out,0}=V_{in}\frac{R_2}{R_1+R_2} =12\frac{6.8}{18+6.8} =3.29\ \text{V}.

With the load attached:

\displaystyle R_2'=R_2\parallel R_L =\frac{6.8(20)}{6.8+20} =5.07\ \text{k}\Omega.

The loaded output is:

\displaystyle V_{out,L}=12\frac{5.07}{18+5.07} =2.64\ \text{V}.

The Thevenin resistance seen from the unloaded divider output is:

\displaystyle R_{th}=R_1\parallel R_2 =\frac{18(6.8)}{18+6.8} =4.94\ \text{k}\Omega.

Engineering Comment

The load is only about four times the divider Thevenin resistance, so it pulls the output down strongly. This divider is not a low-impedance reference for a variable or moderately heavy load.

Plausibility Check

The loaded output must be lower than the unloaded output because the load is effectively in parallel with the lower resistor. The drop from $3.29\ \text{V}$ to $2.64\ \text{V}$ is plausible for a $20\ \text{k}\Omega$ load.

Exercise 2: Bias current through a pull-up resistor

A digital-compatible analog status node is pulled up to:

V_S=5.0\ \text{V}

through:

R_P=47\ \text{k}\Omega.

An input leakage current of:

I_L=8\ \mu\text{A}

flows out of the node into a fault-monitoring input. Find the node voltage and decide whether it remains above a required high threshold:

V_{IH}=4.2\ \text{V}.

Solution

The voltage drop across the pull-up resistor is:

\Delta V=I_LR_P =8\ \mu\text{A}\cdot 47\ \text{k}\Omega =0.376\ \text{V}.

The node voltage is:

V_N=5.0-0.376=4.624\ \text{V}.

Compare with the threshold:

4.624\ \text{V}>4.2\ \text{V}.

The node passes the high-level requirement.

Engineering Comment

Leakage is often ignored in nominal schematics, but it matters for high-value resistors, hot temperature, contamination, protection devices and low-power inputs. The margin here is:

4.624-4.2=0.424\ \text{V}.

That is acceptable for this stated leakage, but the design should still check maximum leakage over temperature and board contamination.

Plausibility Check

An $8\ \mu\text{A}$ leakage through tens of kilohms creates a few tenths of a volt drop, not millivolts and not several volts. The result is in the expected range.

Exercise 3: Series resistor for an LED indicator

An indicator LED is powered from:

V_S=5.0\ \text{V}.

The LED forward voltage at the target current is:

V_F=2.1\ \text{V}

and the desired current is:

I_D=8\ \text{mA}.

Find the required series resistance and the resistor power dissipation.

Solution

The resistor must drop:

V_R=V_S-V_F=5.0-2.1=2.9\ \text{V}.

The resistance is:

\displaystyle R=\frac{V_R}{I_D} =\frac{2.9}{0.008} =362.5\ \Omega.

A standard value of $360\ \Omega$ is a close first choice.

The resistor power is:

P_R=I_D^2R =(0.008)^2(362.5) =0.0232\ \text{W}.

Engineering Comment

A $0.125\ \text{W}$ resistor is sufficient for this nominal condition, but the LED current should be checked at supply tolerance, LED forward-voltage tolerance and temperature. The LED current is not set by the nominal forward voltage alone.

Plausibility Check

An $8\ \text{mA}$ indicator from a $5\ \text{V}$ rail usually uses a resistor in the few-hundred-ohm range. A dissipation near $23\ \text{mW}$ is consistent with a low-current indicator.

Exercise 4: Zener shunt reference worst-case power

A simple zener shunt reference uses:

V_Z=3.3\ \text{V},\qquad R_S=390\ \Omega.

The input can reach:

V_{in,\max}=12\ \text{V}.

At the same time, the load current may fall to:

I_{L,\min}=2\ \text{mA}.

Find the series current, zener current and zener power at this worst-case condition. The zener package limit is:

P_{Z,\max}=250\ \text{mW}.

Solution

The series current is:

\displaystyle I_S=\frac{V_{in,\max}-V_Z}{R_S} =\frac{12-3.3}{390} =0.0223\ \text{A}.

So:

I_S=22.3\ \text{mA}.

The zener current is the series current minus load current:

I_Z=22.3-2.0=20.3\ \text{mA}.

The zener power is:

P_Z=V_ZI_Z =3.3(0.0203) =0.067\ \text{W}.

So:

P_Z=67\ \text{mW}.

The zener is below the $250\ \text{mW}$ limit for this DC case.

Engineering Comment

This check does not prove the reference is accurate. Zener voltage tolerance, dynamic resistance, minimum zener current, load transients and temperature coefficient still matter. The result only shows that the selected part is not overloaded in the stated worst-case power condition.

Plausibility Check

The zener current is around $20\ \text{mA}$ and the voltage is $3.3\ \text{V}$ , so a power near $66\ \text{mW}$ is expected.

Exercise 5: Diode clamp current during an input fault

An analog input has a series resistor:

R_S=2.2\ \text{k}\Omega.

A clamp diode conducts to a $3.3\ \text{V}$ rail when the input pin rises about:

V_D=0.7\ \text{V}

above the rail. A field wiring fault applies:

V_{fault}=12\ \text{V}.

Estimate the clamp current and decide whether it is below a continuous clamp-current guideline of:

I_{\max}=5\ \text{mA}.

Solution

The clamped input node is approximately:

V_C=3.3+0.7=4.0\ \text{V}.

The series resistor voltage is:

V_R=12-4.0=8.0\ \text{V}.

The clamp current is:

\displaystyle I_C=\frac{8.0}{2.2\ \text{k}\Omega} =3.64\ \text{mA}.

This is below:

5\ \text{mA}.

Engineering Comment

The current limit passes, but the rail must be able to absorb or route the injected current. If the rail is lightly loaded, the clamp current can raise the supply unless a regulator, TVS, shunt path or protection scheme handles it.

Plausibility Check

Several volts across a few kilohms should produce a few milliamps. The computed $3.64\ \text{mA}$ is physically reasonable.

Exercise 6: Inverting op-amp gain and output swing

An inverting amplifier uses:

R_{in}=10\ \text{k}\Omega,\qquad R_f=68\ \text{k}\Omega.

The input is a sine wave with peak amplitude:

V_{in,pk}=0.25\ \text{V}.

The op-amp output swing is limited to:

\pm 3.8\ \text{V}.

Find the ideal gain, output peak amplitude and swing margin.

Solution

The ideal inverting gain is:

\displaystyle A_v=-\frac{R_f}{R_{in}} =-\frac{68}{10} =-6.8.

The output peak amplitude is:

V_{out,pk}=|A_v|V_{in,pk} =6.8(0.25) =1.70\ \text{V}.

The swing margin to the output limit is:

3.8-1.70=2.10\ \text{V}.

Engineering Comment

The ideal gain and swing pass. A real review should still check input common-mode range, input bias current through the resistor network, noise, offset, stability with source capacitance and whether the next stage can accept the inverted signal polarity.

Plausibility Check

A gain near seven applied to a quarter-volt signal should produce less than $2\ \text{V}$ peak. That is comfortably inside a nearly $4\ \text{V}$ output-swing limit.

Exercise 7: Non-inverting op-amp bandwidth and slew-rate check

A non-inverting amplifier has:

R_f=90\ \text{k}\Omega,\qquad R_g=10\ \text{k}\Omega.

The op-amp gain-bandwidth product is:

GBW=1.0\ \text{MHz}.

The signal frequency is:

f=20\ \text{kHz}

and the required output peak amplitude is:

V_{pk}=2.0\ \text{V}.

The op-amp slew-rate limit is:

SR_{\max}=0.35\ \text{V}/\mu\text{s}.

Check closed-loop bandwidth and slew rate.

Solution

The non-inverting gain is:

\displaystyle A_v=1+\frac{R_f}{R_g} =1+\frac{90}{10} =10.

The approximate closed-loop bandwidth is:

\displaystyle f_{CL}\approx \frac{GBW}{A_v} =\frac{1.0\ \text{MHz}}{10} =100\ \text{kHz}.

The bandwidth is above the signal frequency:

100\ \text{kHz}>20\ \text{kHz}.

The sine-wave slew-rate requirement is:

SR=2\pi fV_{pk} =2\pi(20{,}000)(2.0) =251{,}000\ \text{V/s}.

Convert to volts per microsecond:

251{,}000\ \text{V/s}=0.251\ \text{V}/\mu\text{s}.

The slew-rate requirement is below:

0.35\ \text{V}/\mu\text{s}.

Both first-pass checks pass.

Engineering Comment

The bandwidth margin is not the same as a distortion guarantee. Closed-loop gain flatness, phase shift, load capacitance, noise gain, layout and large-signal output current can still make the circuit unacceptable.

Plausibility Check

A gain of ten from a $1\ \text{MHz}$ op-amp gives a bandwidth around $100\ \text{kHz}$ . A $20\ \text{kHz}$ , $2\ \text{V}$ peak sine wave needs a fraction of a volt per microsecond, so the result is plausible.

Exercise 8: Input bias current error in a high-resistance amplifier

An inverting amplifier uses:

R_f=1.0\ \text{M}\Omega.

The op-amp input bias current is:

I_B=35\ \text{nA}.

Estimate the output offset contribution from bias current through the feedback resistor. The allowable output offset budget for this source is:

V_{off,\max}=20\ \text{mV}.

Solution

The bias-current output error is approximately:

V_{off}=I_BR_f.

Substitute:

V_{off}=35\ \text{nA}\cdot 1.0\ \text{M}\Omega =35\ \text{mV}.

Compare with the budget:

35\ \text{mV}>20\ \text{mV}.

The design fails this offset budget.

Engineering Comment

High feedback resistance can be attractive for low sensor loading, but it makes bias current, leakage, board contamination and input protection leakage visible. A lower-bias op-amp, lower resistor values, compensation resistor or different topology may be required.

Plausibility Check

Nanoamps times megaohms gives millivolts to tens of millivolts. The computed $35\ \text{mV}$ is in the expected range and large enough to matter for precision analog work.

Exercise 9: RC low-pass cutoff and interference attenuation

A first-order RC low-pass filter uses:

R=3.3\ \text{k}\Omega,\qquad C=10\ \text{nF}.

Find the cutoff frequency and the magnitude at an interference frequency:

f_i=20\ \text{kHz}.

Use:

\displaystyle |H(f)|=\frac{1}{\sqrt{1+(f/f_c)^2}}.

Solution

The cutoff frequency is:

\displaystyle f_c=\frac{1}{2\pi RC} =\frac{1}{2\pi(3.3\ \text{k}\Omega)(10\ \text{nF})} =4823\ \text{Hz}.

At $20\ \text{kHz}$ :

\displaystyle \frac{f_i}{f_c}=\frac{20{,}000}{4823}=4.15.

The magnitude is:

\displaystyle |H|=\frac{1}{\sqrt{1+4.15^2}} =0.234.

In decibels:

20\log_{10}(0.234)=-12.6\ \text{dB}.

Engineering Comment

A first-order filter gives only moderate attenuation one decade above cutoff. If the interference must be strongly rejected, the design may need a lower cutoff, higher-order filter, shielding, differential measurement or layout correction.

Plausibility Check

At roughly four times cutoff, a first-order low-pass should attenuate by a little more than $12\ \text{dB}$ . The result matches that expectation.

Exercise 10: RC settling before an ADC sample

A sensor signal passes through a source resistance and filter that create:

R=12\ \text{k}\Omega,\qquad C=4.7\ \text{nF}.

After a multiplexer switch, the sampling circuit requires the node to settle within $1\%$ of final value. Estimate the required settling time using:

e^{-t/RC}\le 0.01.

The available acquisition time is:

t_{acq}=180\ \mu\text{s}.

Does it pass?

Solution

The time constant is:

\tau=RC=(12\ \text{k}\Omega)(4.7\ \text{nF}) =56.4\ \mu\text{s}.

For $1\%$ settling:

t\ge -RC\ln(0.01).

Since:

-\ln(0.01)=4.605,

the required time is:

t\ge 4.605(56.4\ \mu\text{s}) =260\ \mu\text{s}.

The available time is only:

180\ \mu\text{s}<260\ \mu\text{s}.

The acquisition-time check fails.

Engineering Comment

This is a common boundary between analog and mixed-signal design. The filter may look harmless in a schematic, but the ADC sampling schedule can turn it into a measurement error. Options include more acquisition time, lower source resistance, smaller capacitance, buffering or a slower scan rate.

Plausibility Check

One-percent settling requires about $4.6$ time constants. With a $56.4\ \mu\text{s}$ time constant, the required time should be a few hundred microseconds. The computed value is consistent.

Exercise 11: Resistor thermal-noise estimate

A high-value sensor resistor is:

R=100\ \text{k}\Omega.

The measurement bandwidth is:

B=1.0\ \text{kHz}

at room temperature:

T=300\ \text{K}.

Estimate the RMS thermal noise voltage:

v_n=\sqrt{4kTRB}

using:

k=1.38\times 10^{-23}\ \text{J/K}.

Solution

Substitute:

v_n=\sqrt{4(1.38\times10^{-23})(300)(100{,}000)(1000)}.

Inside the square root:

4kTRB=1.656\times 10^{-12}.

Therefore:

v_n=\sqrt{1.656\times10^{-12}} =1.29\times10^{-6}\ \text{V}.

So:

v_n=1.29\ \mu\text{V RMS}.

Engineering Comment

The resistor alone is not the full noise budget. Amplifier voltage noise, current noise, bandwidth shape, shielding, reference noise, quantization and interference can dominate. Still, resistor noise is a useful lower-bound check.

Plausibility Check

Thermal noise for a $100\ \text{k}\Omega$ resistor over $1\ \text{kHz}$ should be on the order of microvolts RMS. The result is plausible.

Exercise 12: SNR from signal and noise voltages

An analog front end produces a sine-wave signal with RMS amplitude:

V_s=0.80\ \text{V RMS}.

The measured broadband noise at the same point is:

V_n=2.5\ \text{mV RMS}.

Assuming equal impedance, find:

\displaystyle SNR_{dB}=20\log_{10}\left(\frac{V_s}{V_n}\right).

The requirement is:

SNR_{dB}\ge 48\ \text{dB}.

Solution

The voltage ratio is:

\displaystyle \frac{V_s}{V_n}=\frac{0.80}{0.0025}=320.

The SNR is:

SNR_{dB}=20\log_{10}(320) =50.1\ \text{dB}.

Compare with the requirement:

50.1\ \text{dB}>48\ \text{dB}.

The SNR passes with:

50.1-48=2.1\ \text{dB}

of margin.

Engineering Comment

The pass margin is modest. If the noise measurement was taken at room temperature only, or without the final enclosure and cable harness, this result should not be treated as final release evidence.

Plausibility Check

A voltage ratio of $100$ is $40\ \text{dB}$ and a ratio of $1000$ is $60\ \text{dB}$ . A ratio of $320$ should be close to $50\ \text{dB}$ .

Exercise 13: Worst-case and RSS tolerance budget

An analog gain stage has four independent first-pass error contributors:

Contributor	Error
Resistor ratio tolerance	$1.2\%$
Op-amp offset referred to output	$0.6\%$
Reference tolerance	$0.8\%$
Temperature drift over range	$1.0\%$

Compute the worst-case sum and the root-sum-square estimate. The design target is:

|e|\le 2.5\%.

Solution

The worst-case sum is:

E_{wc}=1.2+0.6+0.8+1.0=3.6\%.

The RSS estimate is:

E_{rss}=\sqrt{1.2^2+0.6^2+0.8^2+1.0^2}.

Calculate:

E_{rss}=\sqrt{1.44+0.36+0.64+1.00} =\sqrt{3.44} =1.85\%.

Worst-case fails the $2.5\%$ target, while RSS passes.

Engineering Comment

RSS can be useful when errors are independent and distributions are justified. It is not a substitute for a guaranteed limit. If the requirement is contractual or safety-critical, the worst-case failure matters.

Plausibility Check

The RSS value should be smaller than the arithmetic sum and larger than the largest single contributor. It is $1.85\%$ , which is larger than $1.2\%$ and smaller than $3.6\%$ .

Exercise 14: Junction temperature of a linear regulator

A linear regulator drops:

V_{in}=12\ \text{V}

to:

V_{out}=5.0\ \text{V}

at load current:

I=120\ \text{mA}.

The ambient temperature is:

T_A=55\ \text{deg C}

and the junction-to-ambient thermal resistance on the actual board is estimated as:

\theta_{JA}=62\ \text{deg C/W}.

Find the regulator power dissipation and junction temperature. The release limit is:

T_{J,\max}=110\ \text{deg C}.

Solution

The voltage drop is:

V_D=12-5=7\ \text{V}.

The power dissipation is:

P_D=V_DI=7(0.120)=0.84\ \text{W}.

The temperature rise is:

\Delta T=P_D\theta_{JA} =0.84(62) =52.1\ \text{deg C}.

The junction temperature is:

T_J=T_A+\Delta T =55+52.1 =107.1\ \text{deg C}.

The margin is:

110-107.1=2.9\ \text{deg C}.

The check barely passes.

Engineering Comment

A $2.9\ \text{deg C}$ thermal margin is weak because board copper, enclosure airflow, neighboring heat sources and load tolerance may be uncertain. A switching regulator, lower input voltage, lower load current or better thermal path may be needed for robust release.

Plausibility Check

Dissipating nearly one watt in a small linear regulator can easily create a rise above $50\ \text{deg C}$ . The computed temperature is credible.

Exercise 15: Capacitor impedance at two frequencies

A coupling capacitor has:

C=100\ \text{nF}.

Find its reactance magnitude at:

f_1=100\ \text{Hz}

and:

f_2=100\ \text{kHz}.

Use:

\displaystyle |Z_C|=\frac{1}{2\pi fC}.

Solution

At $100\ \text{Hz}$ :

\displaystyle |Z_C|=\frac{1}{2\pi(100)(100\ \text{nF})} =15.9\ \text{k}\Omega.

At $100\ \text{kHz}$ :

\displaystyle |Z_C|=\frac{1}{2\pi(100{,}000)(100\ \text{nF})} =15.9\ \Omega.

The impedance changes by a factor of:

\displaystyle \frac{15.9\ \text{k}\Omega}{15.9\ \Omega}=1000.

Engineering Comment

The same capacitor can block low-frequency content while passing high-frequency content. In a real board, equivalent series resistance, equivalent series inductance, dielectric type and self-resonant frequency decide whether the capacitor still behaves as intended at high frequency.

Plausibility Check

Increasing frequency by a factor of $1000$ should reduce capacitive reactance by a factor of $1000$ . The result follows that inverse relationship.

Exercise 16: Clamp resistor pulse-energy screen

A protection resistor sees a fault pulse with:

V_R=24\ \text{V}

across:

R=1.0\ \text{k}\Omega.

The pulse duration is:

t=20\ \text{ms}.

Find the pulse current, instantaneous resistor power and pulse energy. The resistor pulse-energy rating for this duration is:

E_{\max}=20\ \text{mJ}.

Solution

The pulse current is:

\displaystyle I=\frac{V_R}{R} =\frac{24}{1000} =24\ \text{mA}.

The instantaneous power is:

\displaystyle P=\frac{V_R^2}{R} =\frac{24^2}{1000} =0.576\ \text{W}.

The pulse energy is:

E=Pt =0.576(0.020) =0.0115\ \text{J}.

So:

E=11.5\ \text{mJ}.

The pulse-energy screen passes because:

11.5\ \text{mJ}<20\ \text{mJ}.

Engineering Comment

Average power is not enough for protection parts. Short pulses can fail a resistor, diode or clamp even when steady-state power looks small. The real rating must come from the correct pulse duration and repetition profile.

Plausibility Check

The instantaneous power is a little over half a watt, but only for $20\ \text{ms}$ , so the energy should be around ten millijoules. The result is consistent.

Exercise 17: Gain drift from resistor temperature coefficients

A non-inverting amplifier has nominal gain:

\displaystyle A_v=1+\frac{R_f}{R_g}=11.

The feedback resistor and gain resistor have unmatched temperature coefficients that can change the ratio by:

80\ \text{ppm/deg C}.

The operating temperature span from calibration is:

\Delta T=70\ \text{deg C}.

Estimate the gain-ratio drift in percent and the output error for:

V_{out}=4.0\ \text{V}.

Solution

The ratio drift is:

80\ \text{ppm/deg C}\cdot 70\ \text{deg C} =5600\ \text{ppm}.

Convert to percent:

5600\ \text{ppm}=0.56\%.

The output error at $4.0\ \text{V}$ is:

\Delta V=0.0056(4.0)=0.0224\ \text{V}.

So:

\Delta V=22.4\ \text{mV}.

Engineering Comment

Matched resistor networks can reduce ratio drift compared with unrelated discrete resistors. This matters when the gain must remain accurate after calibration across temperature.

Plausibility Check

Tens of ppm per degree over tens of degrees gives thousands of ppm, or a fraction of a percent. A fraction of a percent of $4\ \text{V}$ should be tens of millivolts.

Exercise 18: Analog circuit release gate

A prototype analog conditioning circuit has the following validation results:

Check	Requirement	Measured
Gain error after calibration	$\le 1.5\%$	$1.1\%$
Output offset over temperature	$\le 15\ \text{mV}$	$18\ \text{mV}$
SNR at minimum signal	$\ge 48\ \text{dB}$	$50\ \text{dB}$
Junction temperature	$\le 110\ \text{deg C}$	$104\ \text{deg C}$
Fault clamp pulse-energy test	required	not performed

Should the circuit be released?

Solution

Check each requirement.

Gain error passes:

1.1\%<1.5\%.

Offset fails:

18\ \text{mV}>15\ \text{mV}.

SNR passes:

50\ \text{dB}>48\ \text{dB}.

Junction temperature passes:

104\ \text{deg C}<110\ \text{deg C}.

The fault clamp pulse-energy test is missing. Since it is required evidence, release must be held.

The circuit should not be released until the offset drift is corrected or justified and the clamp pulse-energy test is completed.

Engineering Comment

Release is not an average score. A circuit that has good SNR and acceptable temperature can still fail if offset exceeds the measurement budget or if the protection circuit has not been validated under fault energy.

Plausibility Check

Three rows pass, one row fails numerically and one required test is missing. The only defensible decision is hold.

Review Checklist

Before accepting an analog circuit or electronic-device stage, check:

supply range, load range, temperature range and fault cases;
divider loading, source impedance and Thevenin resistance;
diode, zener and clamp current, power and pulse energy;
op-amp gain, input range, output swing, bias current and offset;
bandwidth, slew rate, phase shift and settling time;
resistor noise, amplifier noise, SNR and measurement bandwidth;
worst-case and RSS tolerance assumptions;
junction temperature, derating and package thermal path;
layout-sensitive paths, grounding, leakage and electromagnetic interference;
validation evidence from bench, temperature, production and fault tests.

Common Mistakes

Treating an unloaded divider calculation as the final loaded output.
Using a diode forward voltage without checking current, temperature and power.
Treating a zener reference as accurate just because it survives power.
Checking op-amp gain while ignoring output swing, slew rate or bias current.
Choosing an RC filter without checking ADC acquisition or signal delay.
Reporting SNR without bandwidth and measurement point.
Using RSS tolerance when the requirement needs a guaranteed worst-case limit.
Copying datasheet thermal resistance without matching board conditions.
Designing protection parts for DC power but not pulse energy.
Releasing an analog circuit without fault, temperature and production evidence.

The central habit is to make every analog calculation a release decision. The equation gives a number; engineering judgment decides whether that number is enough for the real circuit, environment and validation evidence.

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