Engineering branch
Computer Engineering
Computer engineering entries covering data structures, algorithms, architecture, operating systems, distributed systems, embedded hardware, and firmware reliability.
Entries · 26
Topic Algorithmic Performance and Data Structures A practical introduction to algorithmic performance and data structures, including complexity, latency, memory use, arrays, hash tables, trees, graphs, queues, and engineering trade-offs. Topic Computer Architecture and Memory Systems Computer architecture guide covering processors, memory hierarchy, buses, latency, bandwidth, cache locality, real-time constraints, power, reliability, and validation. Topic Digital Logic and Embedded Computer Systems Computer guide to digital logic, Boolean algebra, microcontrollers, buses, sampling, quantization, firmware timing, control loops, EMI, reliability, and validation. Topic Operating Systems, Concurrency, and Distributed Computing Computer guide to operating systems, concurrency, distributed computing, scheduling, synchronization, ordering, fault tolerance, observability, rollout, and validation. Topic Real-Time Embedded Software and Firmware Reliability Computer guide to embedded firmware reliability: timing budgets, interrupts, scheduling, drivers, diagnostics, communication, fault handling, testing, and validation. Glossary term Aliasing The distortion that occurs when a signal is sampled too slowly or without sufficient filtering, causing high-frequency content to appear as false lower-frequency content. Glossary term Binary Tree A hierarchical data structure in which each node has at most two child nodes, commonly called the left and right child. Glossary term Boolean Algebra The algebra of two-valued logic used to represent, simplify, and verify logical operations in digital and computational systems. Glossary term Data Bus A shared communication pathway that transfers data between components, subsystems, or devices in a digital or embedded system. Glossary term Digital Twin A digital representation of a physical asset, process, or system that is updated with operational data to support analysis, prediction, control, or decision-making. Glossary term K-Means Clustering An unsupervised learning method that partitions data into k clusters by minimizing within-cluster squared distance to centroids. Glossary term Latency The elapsed time between a cause and its observable effect in a computing, communication, measurement, or control system. Glossary term Logic Gate A digital circuit element that implements a Boolean operation on one or more input signals. Glossary term Machine Learning A family of computational methods that learn patterns or decision rules from data rather than being fully programmed by explicit rules. Glossary term Microcontroller A compact integrated circuit containing a processor, memory, and peripherals for embedded control. Glossary term Neural Network A computational model made of connected units whose parameters are trained from data. Glossary term Quantization The mapping of a continuous range of values into a finite set of discrete levels. Glossary term XHTML An XML serialization of HTML that requires well-formed markup and stricter document structure. Glossary term XOR Gate A digital logic gate whose output is true when inputs differ, commonly used for parity, adders, and bitwise comparison. Formula sheet Algorithmic Performance Formula Sheet Core formulas and checks for algorithmic performance: Big O growth, loops, memory footprint, amortized cost, queueing, throughput, latency percentiles, and reliability. Formula sheet Digital Logic and Embedded Systems Formula Sheet Digital logic formulas for Boolean laws, timing, I/O margins, buffers, bus bandwidth, sampling, quantization, latency, jitter, watchdogs, power, and reliability. Formula sheet Real-Time Task Scheduling Formula Sheet Computer engineering formula sheet for real-time task scheduling, covering utilization, hyperperiods, deadline margin, response-time analysis, rate-monotonic bounds, EDF feasibility, jitter, blocking, queues, watchdog timing, and validation metrics. Project Microcontroller Data Acquisition Project Computer engineering project for designing and validating a microcontroller data-acquisition system, including sensor channels, sampling rates, ADC scaling, anti-alias filtering, buffer sizing, firmware timing, calibration, diagnostics, and validation evidence. Exercise set Cache, Memory, and Performance Exercises Worked computer engineering exercises for cache behavior, memory footprint, average memory access time, locality, bus bandwidth, transfer time, queue utilization, Amdahl speedup, tail latency, and performance-validation evidence. Exercise set Digital Logic and Timing Analysis Exercises Worked computer engineering exercises for digital logic and embedded timing, covering Boolean simplification, propagation delay, setup and hold checks, synchronizers, bus throughput, buffers, sampling, quantization, jitter, interrupt load, timers, PWM, and release evidence. Case study Embedded Watchdog and Fault Recovery Case Study Case study of an embedded motor controller fault-recovery redesign, covering watchdog timing, scheduler blocking, flash logging, safe outputs, reset diagnosis, brown-out behavior, communication faults, and validation evidence.