Exercise set

Mixed-Signal Electronic Systems and EMC Validation Exercises

Worked electronic engineering exercises for mixed-signal systems and EMC validation covering error budgets, SNR, ADC quantization, sampling margin, aliasing, jitter, PDN droop, filter cutoff, common-mode current, thermal rise, RPN, and validation evidence.

Branch: Electronic Engineering
Content: Exercise set
Updated: Jun 20, 2026
Revision: v1.1.0 · reviewed

These exercises practise mixed-signal electronics and EMC validation as system engineering. They cover error budgets, signal-to-noise ratio, ADC quantization, sampling margin, aliasing, jitter, power integrity, filter cutoff, common-mode current, thermal rise, risk priority, and validation evidence.

The goal is not only to calculate an electronic value. The goal is to decide whether analog, digital, power, firmware, PCB layout, cables, enclosure, manufacturing, and validation measurements support the same product requirement.

Assume simplified screening models unless an exercise states otherwise. Real mixed-signal and EMC work should also check component tolerances, layout parasitics, return paths, cable configurations, probe setup, firmware state, environmental exposure, production variation, and compliance test configuration.

How to Use These Exercises

For each exercise, define:

the system function being protected;
the analog, digital, power, cable, enclosure, or firmware path involved;
the frequency, timing, amplitude, or environmental condition that matters;
the measurement method and acceptance limit;
the action if validation evidence is incomplete.

The common mistake is treating mixed-signal design as separate analog, digital, and firmware blocks. The product behaves as one physical system.

For each result, state whether it supports accuracy allocation, sampling architecture, power-integrity margin, EMC mitigation, thermal derating, production-test limit, or validation release. A measurement result is useful only when the probe setup, firmware mode, cable configuration, grounding, and acceptance limit are explicit.

Exercise 1: Error Budget RSS Combination

A sensor measurement chain has independent error contributors:

Source	Error
Sensor tolerance	0.35 percent
Excitation error	0.20 percent
Amplifier offset and drift	0.25 percent
ADC and reference error	0.30 percent

Estimate total root-sum-square error.

Solution

For independent contributors:

E_{RSS}=\sqrt{E_1^2+E_2^2+E_3^2+E_4^2}

Substitute:

E_{RSS}=\sqrt{0.35^2+0.20^2+0.25^2+0.30^2}

E_{RSS}=\sqrt{0.1225+0.0400+0.0625+0.0900}

E_{RSS}=\sqrt{0.3150}=0.561\%

Engineering Comment

The RSS result is lower than a worst-case sum, but it relies on independence and distribution assumptions. Safety-critical, metrology, and regulated systems often require worst-case limits, calibration evidence, temperature coverage, and uncertainty documentation.

Exercise 2: Signal-to-Noise Ratio

A conditioned analog signal has RMS amplitude:

V_s=1.20\ \text{V}

The measured RMS noise is:

V_n=2.0\ \text{mV}

Calculate SNR in decibels:

\displaystyle SNR=20\log_{10}\left(\frac{V_s}{V_n}\right)

Solution

Convert:

V_n=0.0020\ \text{V}

Ratio:

\displaystyle \frac{V_s}{V_n}=\frac{1.20}{0.0020}=600

Therefore:

SNR=20\log_{10}(600)=55.6\ \text{dB}

Engineering Comment

SNR is useful, but it does not include offset, gain error, drift, nonlinearity, saturation, aliasing, or timing error. A measurement system can have good SNR and still fail accuracy if systematic errors dominate.

Exercise 3: ADC Quantization Step

An ADC has:

N=12\ \text{bits}

and input range:

V_{FS}=3.3\ \text{V}

Estimate the ideal quantization step:

\displaystyle q=\frac{V_{FS}}{2^N}

Solution

Number of codes:

2^{12}=4096

Quantization step:

\displaystyle q=\frac{3.3}{4096}=0.000805\ \text{V}

Therefore:

q=0.805\ \text{mV}

Engineering Comment

The 0.805 mV step is not the same as useful accuracy. Reference noise, input settling, layout coupling, source impedance, temperature drift, ADC nonlinearity, and firmware filtering can dominate the error budget.

Exercise 4: Sampling Margin

A sensor signal has required bandwidth:

B=1.8\ \text{kHz}

The ADC sampling frequency is:

f_s=8.0\ \text{kHz}

Use the sampling theorem screen:

f_s>2B

Calculate the margin above the minimum ideal sampling rate.

Solution

Minimum ideal sampling rate:

f_{min}=2B=2(1.8)=3.6\ \text{kHz}

Sampling margin:

M=f_s-f_{min}=8.0-3.6=4.4\ \text{kHz}

Ratio:

\displaystyle \frac{f_s}{f_{min}}=\frac{8.0}{3.6}=2.22

Engineering Comment

The ideal Nyquist condition passes, but the design still needs anti-alias filtering, ADC acquisition-time review, firmware timing control, and phase-delay assessment if the signal is used in feedback.

Exercise 5: Aliased Frequency

A noise component at:

f_{in}=7.2\ \text{kHz}

is sampled at:

f_s=5.0\ \text{kHz}

Estimate the first-order alias frequency using:

f_a=\left|f_{in}-k f_s\right|

with the integer (k) that brings the result into the baseband.

Solution

Choose:

k=1

Then:

f_a=\left|7.2-1(5.0)\right|=2.2\ \text{kHz}

The 7.2 kHz noise can appear as a 2.2 kHz component in sampled data.

Engineering Comment

Aliasing can turn out-of-band switching noise into an in-band measurement error. Anti-alias filters must be designed from the real noise environment, not only from the desired sensor bandwidth.

Exercise 6: Jitter-Limited SNR

An ADC samples a sine-wave input at frequency:

f_{in}=100\ \text{kHz}

Clock RMS jitter is:

t_j=20\ \text{ps}

Estimate jitter-limited SNR:

SNR_j=-20\log_{10}(2\pi f_{in}t_j)

Solution

Convert:

t_j=20\times10^{-12}\ \text{s}

Compute:

2\pi f_{in}t_j=2\pi(100\times10^3)(20\times10^{-12})

2\pi f_{in}t_j=1.26\times10^{-5}

Therefore:

SNR_j=-20\log_{10}(1.26\times10^{-5})=98.0\ \text{dB}

Engineering Comment

At 100 kHz, 20 ps jitter is unlikely to dominate a moderate-resolution measurement. At higher input frequency, jitter can become a primary limit. Clock layout, power noise, PLL configuration, and firmware timing should be reviewed when dynamic accuracy matters.

Exercise 7: PDN Droop from Load Step

A mixed-signal board has a 3.3 V rail. A radio and processor load step is:

\Delta I=0.9\ \text{A}

The estimated PDN impedance at the relevant frequency is:

Z_{PDN}=55\ \text{m}\Omega

Estimate supply droop:

\Delta V=\Delta I Z_{PDN}

Solution

Convert:

Z_{PDN}=0.055\ \Omega

Compute:

\Delta V=0.9(0.055)=0.0495\ \text{V}

Therefore:

\Delta V=49.5\ \text{mV}

Engineering Comment

This droop may disturb ADC references, RF power amplifiers, microcontroller brown-out thresholds, or sensor excitation. Validation should measure the rail at the load pins during real firmware activity, not only at the regulator output.

Exercise 8: RC Low-Pass Cutoff

An analog input filter uses:

R=2.2\ \text{k}\Omega

and:

C=22\ \text{nF}

Estimate cutoff frequency:

\displaystyle f_c=\frac{1}{2\pi RC}

Solution

Convert:

R=2.2\times10^3\ \Omega

C=22\times10^{-9}\ \text{F}

Compute:

\displaystyle f_c=\frac{1}{2\pi(2.2\times10^3)(22\times10^{-9})}

f_c=3.29\ \text{kHz}

Engineering Comment

The filter can reduce out-of-band noise, but it also adds phase delay and source impedance for the ADC. Check sensor bandwidth, sampling frequency, acquisition time, tolerance, and whether switching noise needs a steeper filter.

Exercise 9: Common-Mode Cable Current from Impedance

An EMC pre-scan estimates common-mode voltage on a cable shield:

V_{CM}=0.30\ \text{V}

The common-mode return impedance at the frequency of interest is:

Z_{CM}=15\ \Omega

Estimate common-mode current:

\displaystyle I_{CM}=\frac{V_{CM}}{Z_{CM}}

Solution

Substitute:

\displaystyle I_{CM}=\frac{0.30}{15}=0.020\ \text{A}

Therefore:

I_{CM}=20\ \text{mA}

Engineering Comment

Twenty milliamps of common-mode current can be significant for emissions. Review cable shield bonding, connector pinout, filter placement, enclosure continuity, return path, and whether the noise source is differential-mode current converted into common-mode current.

Exercise 10: Thermal Rise of a Power Device

A power driver dissipates:

P_D=1.4\ \text{W}

The board-level thermal resistance is:

\theta_{JA}=42^\circ\text{C/W}

Ambient temperature is:

T_A=50^\circ\text{C}

Estimate junction temperature.

Solution

Temperature rise:

\Delta T=P_D\theta_{JA}=1.4(42)=58.8^\circ\text{C}

Junction temperature:

T_J=T_A+\Delta T=50+58.8=108.8^\circ\text{C}

Engineering Comment

The estimate is close to typical derating limits for many devices. It should be checked with thermal imaging, copper-area assumptions, enclosure temperature, duty cycle, neighboring heat sources, and fault operation.

Exercise 11: Risk Priority Number for EMC Failure Mode

An EMC-related failure mode has ratings:

S=8

O=4

D=5

where S is severity, O is occurrence, and D is detection rating. Calculate risk priority number:

RPN=SOD

Solution

Compute:

RPN=(8)(4)(5)=160

Engineering Comment

RPN helps rank work, but high severity should receive engineering review even if occurrence appears low. EMC failures can be configuration-dependent, so detection rating should reflect realistic cable, enclosure, grounding, firmware, and operating modes.

Exercise 12: EMC Validation Evidence Completion

A validation plan requires nine evidence items:

conducted emissions scan;
radiated emissions scan;
ESD test at user touch points;
sensor accuracy during actuator switching;
power input disturbance test;
clock and ADC noise measurements;
thermal test during worst-case duty;
communication error recovery test;
production test limits released.

Seven items are complete.

Calculate completion percentage and decide whether release is acceptable if all nine items are mandatory.

Solution

Completion fraction:

\displaystyle f=\frac{7}{9}=0.778

Convert:

f=77.8\%

Because all nine items are mandatory, the release evidence is incomplete.

Engineering Comment

Incomplete EMC evidence is not a paperwork problem. A product can pass bench functionality and still fail in the field because cables, enclosure, ESD paths, firmware state, or actuator noise were not represented in validation.

Review Checklist

When reviewing mixed-signal and EMC evidence, ask:

Does the error budget include offset, drift, quantization, noise, reference error, temperature, and calibration uncertainty?
Are sampling rate, anti-alias filtering, ADC acquisition time, and firmware timing reviewed together?
Are power-rail measurements taken at the load under realistic operating modes?
Are clock, bus, and switching loops routed with controlled return paths?
Are cable shields, connector filters, enclosure bonds, and ESD paths part of the design basis?
Does validation use realistic firmware, cables, loads, enclosure, grounding, and environmental conditions?
Are production tests linked to the failure modes found in design validation?
Are measurement bandwidth, probe loading, grounding method, calibration status, and uncertainty included in the evidence record?
Are compliance pre-scan findings translated into design changes, retest evidence, or explicitly accepted residual risk?

Good mixed-signal engineering makes coupling paths explicit. The system is ready only when analog accuracy, digital timing, power integrity, EMC behavior, firmware state, and validation evidence agree.

REF