Multiplexed ADC Settling Error Case Study

A multiplexed ADC can report a stable but wrong value when the input has not settled before conversion. The error is easy to miss because the ADC code looks digital and repeatable. The cause is analog: the sample-and-hold capacitor still carries charge from the previous channel, and the new sensor source cannot drive it to the correct voltage within the programmed acquisition time.

This case study follows a microcontroller data-acquisition board that alternates between a high-voltage diagnostic channel and a filtered sensor channel. The sensor itself is accurate. The firmware conversion sequence is not. The low channel is biased upward whenever it follows the high channel.

The engineering task is to quantify the settling error in LSBs, compare it with a half-LSB requirement, choose a correction and define validation evidence before release.

Case Context

The board scans several analog channels through a microcontroller ADC. One channel monitors a 3.0\ \text{V} rail. The next channel reads a filtered sensor near 0.8\ \text{V}. The sensor channel uses a resistor-capacitor input filter to reduce noise and electromagnetic pickup.

During validation, the sensor reading depends on scan order. If the sensor is sampled after a low-voltage channel, it is plausible. If it is sampled after the 3.0\ \text{V} diagnostic channel, it reads high.

The central question is:

Is the sensor drifting, or is the ADC input not settling after the multiplexer changes channel?

Failure Signature and Triage

The failure signature is scan-order dependent error. The same sensor voltage produces different codes depending on which channel was sampled immediately before it. That points away from sensor drift, reference error or quantization noise and toward a dynamic input-settling problem.

Useful triage checks are:

• sample the channel repeatedly without switching and compare the first sample with later samples;
• swap the channel order and see whether the error follows the previous voltage step;
• drive the sensor input from a low-impedance calibrator and repeat the scan;
• increase acquisition time in firmware and check whether the bias decays exponentially;
• probe the ADC input pin, not only the sensor output, during the acquisition window.

The key diagnostic clue is repeatability. Random noise moves both directions. Settling error has a sign and magnitude tied to the previous channel voltage.

Design Data

Quantity	Symbol	Value
ADC resolution	N	12\ \text{bit}
ADC reference	V_{ref}	3.3\ \text{V}
previous channel voltage	V_{prev}	3.0\ \text{V}
sensor channel voltage	V_{new}	0.8\ \text{V}
source resistance	R_s	10\ \text{kOhm}
ADC switch resistance	R_{on}	2\ \text{kOhm}
sample capacitor	C_s	20\ \text{pF}
programmed acquisition time	t_{acq}	1.5\ \text{us}
corrected acquisition time	t_{acq,new}	2.5\ \text{us}

The voltage step seen by the sample capacitor is:

Model Assumptions

The first-order model treats the source resistance, ADC switch resistance and sample capacitor as the dominant acquisition path. That is sufficient for a release screen, but the final design review should also check external filter capacitance, op-amp output drive, input leakage, charge injection, ADC data-sheet acquisition definitions, temperature and tolerance of the source network.

The model also assumes the previous channel is the worst-case voltage step. If the firmware scan contains larger high-to-low or low-to-high transitions, the required acquisition time should be recomputed for those steps too.

Step 1: Calculate ADC Code Width

The ideal ADC code width is:

Substitute:

or:

A common settling target is half an LSB:

Engineering Interpretation

The allowed residual error is small. A millivolt-scale analog settling error is several ADC counts on a 12 bit converter.

Step 2: Estimate Input Settling Time Constant

The sample capacitor is charged through source and switch resistance:

Using:

and:

gives:

Step 3: Calculate Residual Settling Error

After acquisition time t_{acq}, the remaining channel-to-channel error is approximated by:

With:

the residual is:

or:

Expressed in ADC counts:

Engineering Interpretation

The error is more than five counts. It is not random noise and it will repeat whenever the scan order creates a large voltage step.

Step 4: Required Acquisition Time

To settle below half an LSB:

Substitute:

so:

The original:

does not meet the half-LSB target.

Step 5: Dummy Conversion Screen

A dummy conversion after the channel switch gives the input another acquisition window before the accepted sample. If the same acquisition time is used twice, the residual after the second acquisition is approximately:

Using (e_s=4.25\ \text{mV}), (t_{acq}=1.5\ \text{us}) and (\tau=0.24\ \text{us}):

In ADC counts:

Engineering Interpretation

A discarded first conversion can be effective, but it costs throughput and must be documented in firmware requirements. It is not a substitute for checking source impedance and acquisition time for every channel class.

Corrective Action

Several corrections are valid depending on speed, noise and hardware constraints:

1. increase ADC acquisition time above 2.07\ \text{us} with margin;
2. reduce source resistance or buffer the channel with a suitable op-amp;
3. add a dummy conversion after large channel steps and discard it;
4. group channels by similar voltage level;
5. verify the RC filter does not make the ADC source impedance too high;
6. use a dedicated ADC driver if speed and accuracy requirements are tight.

With corrected acquisition time:

the residual becomes:

or:

This is comfortably below the half-LSB target.

Correction choice should be driven by the release constraint. If sample throughput has margin, increasing acquisition time is the cleanest firmware fix. If throughput is tight, a dummy conversion may be cheaper than a board change but must be scheduled explicitly. If the channel source impedance is high by design, a buffer amplifier or ADC driver is more robust. If the RC filter is the cause, lowering resistance may increase noise pickup, so the filter and settling requirements must be solved together.

Validation Evidence

Release evidence should include scan-order sensitivity tests, step-response captures at the ADC pin, acquisition-time sweep, dummy-conversion comparison, high-to-low and low-to-high channel transitions, temperature checks, source-impedance tolerance review, ADC data-sheet timing basis and firmware configuration record.

The test should use the final channel order and final firmware. A bench test that samples one channel repeatedly may pass while the deployed multiplexed scan fails.

Minimum validation package:

• a channel-order matrix covering worst-case high-to-low and low-to-high transitions;
• before/after acquisition-time sweep showing exponential error reduction;
• comparison of first sample, dummy sample and accepted sample;
• tolerance case for source resistance, switch resistance and sample capacitance;
• temperature or supply-voltage check if the source network or switch resistance is sensitive;
• firmware record tying acquisition time, scan order and discarded samples to the released build.

Release Decision

The original configuration should not be released because the calculated residual is (5.27\ \text{LSB}), above the half-LSB target. The corrected (2.5\ \text{us}) acquisition time brings the residual to (0.082\ \text{LSB}), which passes the numeric screen.

Release still depends on evidence: the fix must be tested with the final scan order, all production source-impedance tolerances and the actual firmware timing. If the validation only repeats a single channel or uses a lab source with much lower impedance than the field sensor, the release evidence is incomplete.

Common Mistakes

A common mistake is checking ADC bit depth but not acquisition settling. Another is adding an RC filter for noise reduction without checking whether the ADC sample capacitor can charge fast enough through the added source impedance.

Other mistakes include validating channels one at a time, ignoring previous-channel voltage, assuming the ADC input is infinite impedance during acquisition, hiding scan-order error with averaging and changing firmware sample time without updating the validation record. A strong mixed-signal review states source impedance, sample capacitor, acquisition time, channel order, allowed LSB error, filter values and release evidence.