Project

Microcontroller Data Acquisition Project

Computer engineering project for designing and validating a microcontroller data-acquisition system, including sensor channels, sampling rates, ADC scaling, anti-alias filtering, buffer sizing, firmware timing, calibration, diagnostics, and validation evidence.

This project designs and validates a microcontroller-based data acquisition system. The goal is to produce an engineering deliverable that connects sensor requirements, analog interfaces, sampling theory, ADC scaling, firmware timing, buffers, calibration, diagnostics, and validation evidence.

The project can be completed for a laboratory test rig, motor-drive monitor, environmental station, small industrial controller, biomedical prototype, or educational embedded system. The important point is not the specific board. The important point is whether the measured values are trustworthy, timestamped, bounded in latency, and recoverable under faults.

Project Objective

Design a microcontroller data acquisition system that answers:

  1. Which physical quantities are measured?
  2. What range, bandwidth, accuracy, and sampling rate are required?
  3. How are analog signals scaled, filtered, protected, and converted?
  4. How are digital timing signals captured?
  5. How much data rate and buffer memory are required?
  6. Which firmware timing path controls latency and jitter?
  7. How are calibration, diagnostics, and fault recovery handled?
  8. Which tests prove that the acquired data are valid?

The final deliverable should be a design-review package, not only a schematic or code listing.

Baseline Scenario

Use this baseline scenario or replace it with measured project data.

A microcontroller monitors a small motorized test rig. The system records temperature, supply voltage, vibration, and shaft speed while also reporting health status to a host computer.

Measurement channels:

ChannelSensor or signalRangeRequired bandwidthEngineering purpose
TemperatureThermocouple interface0 to 120^\circ\text{C}2\ \text{Hz}Thermal drift and safety limit.
Supply voltageScaled analog input0 to 30\ \text{V}20\ \text{Hz}Brown-out and load transient evidence.
VibrationAnalog accelerometer\pm 4g400\ \text{Hz}Bearing and imbalance screening.
Shaft speedQuadrature encoder0 to 6000\ \text{rpm}event-basedSpeed and missed-pulse detection.

The microcontroller has a 12-bit ADC, timer capture inputs, DMA support, 96\ \text{kB} RAM, and a serial link to the host.

Step 1: Define the Measurement Contract

Each channel needs a data contract:

FieldExample requirement
UnitsTemperature in ^\circ\text{C}, voltage in V, acceleration in g, speed in rpm.
RangeValid operating range and fault range.
SamplingSample rate, timestamp basis, and synchronization rule.
ScalingSensor gain, offset, divider ratio, and calibration coefficients.
FilteringAnalog anti-alias filter and digital filter if used.
DiagnosticsOpen sensor, saturation, stale sample, out-of-range value, and communication loss.
EvidenceCalibration record, timing trace, ADC noise measurement, and fault-injection result.

A data acquisition system is credible only if a number in memory can be traced back to a physical signal, a scaling rule, a timestamp, and a validation method.

Step 2: Choose Sampling Rates

Use the sampling theorem as a first screen:

f_s>2B

For the vibration channel:

B=400\ \text{Hz}

Minimum ideal sample rate:

f_s>800\ \text{Hz}

Choose:

f_s=2000\ \text{Hz}

This gives margin for filter roll-off and timing imperfections.

For slow channels, choose lower rates:

ChannelSelected sample rate
Temperature10\ \text{Hz}
Supply voltage100\ \text{Hz}
Vibration2000\ \text{Hz}
Encoder speed calculation100\ \text{Hz} update from timer captures

The rates should be justified by signal bandwidth, control needs, storage limits, and diagnostic requirements.

Step 3: ADC Scaling

The ADC has:

N=12\ \text{bits}

and reference:

V_{ref}=3.3\ \text{V}

Ideal least significant bit:

\displaystyle LSB=\frac{V_{ref}}{2^N}=\frac{3.3}{4096}=0.806\ \text{mV}

The supply-voltage channel scales 0 to 30\ \text{V} into 0 to 3.0\ \text{V}. The divider ratio is:

\displaystyle k=\frac{3.0}{30}=0.10

One ADC count corresponds to input-voltage change:

\displaystyle LSB_{input}=\frac{0.806\ \text{mV}}{0.10}=8.06\ \text{mV}

Engineering Interpretation

The quantization step is much smaller than many supply-voltage diagnostic thresholds, so ADC resolution is probably adequate. The actual accuracy still depends on resistor tolerance, reference accuracy, ADC offset, noise, input settling, protection leakage, and calibration.

Step 4: Anti-Alias Filter Check

For the vibration channel, choose a first-order RC low-pass filter with:

R=3.3\ \text{k}\Omega

and:

C=47\ \text{nF}

The cutoff frequency is:

\displaystyle f_c=\frac{1}{2\pi RC}

Substitute:

\displaystyle f_c=\frac{1}{2\pi(3300)(47\times10^{-9})}=1026\ \text{Hz}

This cutoff is above the required 400\ \text{Hz} vibration bandwidth and below the 1000\ \text{Hz} Nyquist frequency for a 2000\ \text{Hz} sample rate.

Engineering Interpretation

A first-order filter provides limited attenuation near Nyquist. If high-frequency vibration or switching noise is significant, use a steeper analog filter, increase sampling rate, or prove that aliasing is acceptable for the measurement purpose.

Step 5: Data Rate

Assume each stored sample includes:

  • 16-bit ADC value or speed value;
  • 32-bit timestamp or sample counter;
  • 16-bit status field.

Per sample:

S_{sample}=2+4+2=8\ \text{bytes}

Data rate:

ChannelRateBytes/sampleData rate
Temperature10\ \text{Hz}880\ \text{B/s}
Supply voltage100\ \text{Hz}8800\ \text{B/s}
Vibration2000\ \text{Hz}816000\ \text{B/s}
Speed update100\ \text{Hz}8800\ \text{B/s}

Total:

R_{data}=17680\ \text{B/s}

So the system produces about:

17.7\ \text{kB/s}

before packet framing, metadata, retries, and logs.

Step 6: Buffer Sizing

If the host link can pause for:

t_{gap}=0.5\ \text{s}

required buffer storage is:

B_{req}=R_{data}t_{gap}
B_{req}=17680(0.5)=8840\ \text{bytes}

Add 50\% margin:

B_{buffer}=1.5(8840)=13260\ \text{bytes}

A practical choice is:

B_{buffer}=16\ \text{kB}

Engineering Interpretation

The buffer fits in 96\ \text{kB} RAM, but the memory budget must also include stack, DMA descriptors, communication buffers, calibration tables, logs, and firmware update state. Buffer overflow policy must be defined before testing.

Step 7: Firmware Timing Budget

The high-rate vibration acquisition runs every:

\displaystyle T_s=\frac{1}{2000}=0.5\ \text{ms}

Assume the acquisition interrupt and DMA service path takes:

C_{acq}=35\ \mu\text{s}

The host packetization task runs every 10\ \text{ms} and takes:

C_{packet}=600\ \mu\text{s}

The health monitor runs every 20\ \text{ms} and takes:

C_{health}=180\ \mu\text{s}

CPU utilization screen:

\displaystyle U=\frac{35}{500}+\frac{600}{10000}+\frac{180}{20000}
U=0.070+0.060+0.009=0.139

So the scheduled workload uses about:

U=13.9\%

before other firmware.

Engineering Interpretation

The utilization screen is comfortable, but timing still needs measurement. ADC trigger jitter, DMA contention, disabled interrupts, serial bursts, flash writes, and diagnostic logging can disturb acquisition even when average CPU load is low.

Step 8: Encoder Speed Calculation

Use a quadrature encoder with:

N_{lines}=1024

and 4\times decoding:

m=4

Counts per revolution:

N_c=N_{lines}m=4096

At:

6000\ \text{rpm}=100\ \text{rev/s}

count frequency is:

f_c=N_c(100)=409600\ \text{counts/s}

Engineering Interpretation

The timer capture or counter hardware must handle about 410\ \text{kcounts/s} with margin. Do not service every edge with a long interrupt routine if the microcontroller cannot bound the latency. Hardware counters and periodic reads are often safer.

Step 9: Error Budget

For the supply-voltage channel, define a simplified worst-case error:

ContributorError
Divider tolerance after calibration30\ \text{mV}
ADC reference error20\ \text{mV}
ADC noise and quantization10\ \text{mV}
Input leakage and protection15\ \text{mV}

Worst-case sum:

e_{WC}=30+20+10+15=75\ \text{mV}

Root-sum-square estimate:

e_{RSS}=\sqrt{30^2+20^2+10^2+15^2}=40.3\ \text{mV}

Engineering Interpretation

If the brown-out diagnostic threshold has only 50\ \text{mV} margin, this measurement chain is not good enough without better calibration or filtering. If the threshold margin is 500\ \text{mV}, the channel may be adequate.

Step 10: Firmware Architecture

Use a bounded firmware structure:

  1. hardware timer triggers ADC conversions;
  2. DMA moves samples into a ring buffer;
  3. a short acquisition handler records timestamps and status flags;
  4. a packet task drains the buffer to the host link;
  5. a health monitor checks buffer fill, missed samples, ADC overruns, encoder errors, and watchdog conditions;
  6. calibration data are versioned and protected by integrity checks;
  7. fault states stop acquisition or mark data invalid rather than silently reporting stale values.

The host protocol should include sequence numbers. Missing sequence numbers are often more useful than a vague “communication failed” flag.

Step 11: Diagnostics and Fault Handling

Define diagnostic responses:

FaultDetectionResponse
ADC overrunhardware flag or missed DMA eventmark data invalid, increment counter, alert host.
Buffer near fullhigh-water markthrottle low-priority data or assert backpressure.
Sensor saturationADC near rail for defined durationflag sensor fault, preserve raw counts.
Thermocouple openinterface diagnostic or implausible valuereport invalid temperature and safe status.
Encoder count jumpspeed plausibility checkflag speed data and request inspection.
Host communication losstimeoutcontinue bounded local buffer, then drop by defined policy.
Brown-outvoltage monitor and reset recorddisable outputs, preserve reset cause, restart in safe mode.

Fault handling should preserve evidence. Dropping data may be acceptable; silently reporting old data is usually not.

Step 12: Validation Plan

Validation should include:

  1. ADC scaling check at multiple known input voltages;
  2. frequency-response check for the vibration channel;
  3. anti-alias test with out-of-band signal;
  4. timestamp jitter measurement under communication load;
  5. buffer-overflow and host-pause test;
  6. encoder speed comparison against a reference tachometer;
  7. calibration load, corruption, and version-mismatch tests;
  8. brown-out and watchdog recovery tests;
  9. EMI or switching-noise exposure if the system operates near motors or power converters;
  10. long-duration logging with sequence-number audit.

Each validation result should state equipment used, operating conditions, firmware build, calibration version, sample count, and pass/fail criteria.

Project Deliverables

The final project report should include:

  • measurement requirements and channel table;
  • analog front-end and protection assumptions;
  • sampling-rate justification;
  • ADC scaling and error budget;
  • anti-alias filter calculation;
  • data-rate and buffer-size calculation;
  • firmware timing budget;
  • encoder count-rate check;
  • diagnostics and safe fault responses;
  • validation plan and representative results;
  • known limitations and next design revision.

A strong data acquisition project does not end at “the ADC reads values.” It proves that the values represent the intended physical signals with known timing, bounded uncertainty, controlled failure behavior, and enough evidence for another engineer to trust the data.

REF

See also