Project
Microcontroller Data Acquisition Project
Computer engineering project for designing and validating a microcontroller data-acquisition system, including sensor channels, sampling rates, ADC scaling, anti-alias filtering, buffer sizing, firmware timing, calibration, diagnostics, and validation evidence.
This project designs and validates a microcontroller-based data acquisition system. The goal is to produce an engineering deliverable that connects sensor requirements, analog interfaces, sampling theory, ADC scaling, firmware timing, buffers, calibration, diagnostics, and validation evidence.
The project can be completed for a laboratory test rig, motor-drive monitor, environmental station, small industrial controller, biomedical prototype, or educational embedded system. The important point is not the specific board. The important point is whether the measured values are trustworthy, timestamped, bounded in latency, and recoverable under faults.
Project Objective
Design a microcontroller data acquisition system that answers:
- Which physical quantities are measured?
- What range, bandwidth, accuracy, and sampling rate are required?
- How are analog signals scaled, filtered, protected, and converted?
- How are digital timing signals captured?
- How much data rate and buffer memory are required?
- Which firmware timing path controls latency and jitter?
- How are calibration, diagnostics, and fault recovery handled?
- Which tests prove that the acquired data are valid?
The final deliverable should be a design-review package, not only a schematic or code listing.
Baseline Scenario
Use this baseline scenario or replace it with measured project data.
A microcontroller monitors a small motorized test rig. The system records temperature, supply voltage, vibration, and shaft speed while also reporting health status to a host computer.
Measurement channels:
| Channel | Sensor or signal | Range | Required bandwidth | Engineering purpose |
|---|---|---|---|---|
| Temperature | Thermocouple interface | 0 to 120^\circ\text{C} | 2\ \text{Hz} | Thermal drift and safety limit. |
| Supply voltage | Scaled analog input | 0 to 30\ \text{V} | 20\ \text{Hz} | Brown-out and load transient evidence. |
| Vibration | Analog accelerometer | \pm 4g | 400\ \text{Hz} | Bearing and imbalance screening. |
| Shaft speed | Quadrature encoder | 0 to 6000\ \text{rpm} | event-based | Speed and missed-pulse detection. |
The microcontroller has a 12-bit ADC, timer capture inputs, DMA support, 96\ \text{kB} RAM, and a serial link to the host.
Step 1: Define the Measurement Contract
Each channel needs a data contract:
| Field | Example requirement |
|---|---|
| Units | Temperature in ^\circ\text{C}, voltage in V, acceleration in g, speed in rpm. |
| Range | Valid operating range and fault range. |
| Sampling | Sample rate, timestamp basis, and synchronization rule. |
| Scaling | Sensor gain, offset, divider ratio, and calibration coefficients. |
| Filtering | Analog anti-alias filter and digital filter if used. |
| Diagnostics | Open sensor, saturation, stale sample, out-of-range value, and communication loss. |
| Evidence | Calibration record, timing trace, ADC noise measurement, and fault-injection result. |
A data acquisition system is credible only if a number in memory can be traced back to a physical signal, a scaling rule, a timestamp, and a validation method.
Step 2: Choose Sampling Rates
Use the sampling theorem as a first screen:
For the vibration channel:
Minimum ideal sample rate:
Choose:
This gives margin for filter roll-off and timing imperfections.
For slow channels, choose lower rates:
| Channel | Selected sample rate |
|---|---|
| Temperature | 10\ \text{Hz} |
| Supply voltage | 100\ \text{Hz} |
| Vibration | 2000\ \text{Hz} |
| Encoder speed calculation | 100\ \text{Hz} update from timer captures |
The rates should be justified by signal bandwidth, control needs, storage limits, and diagnostic requirements.
Step 3: ADC Scaling
The ADC has:
and reference:
Ideal least significant bit:
The supply-voltage channel scales 0 to 30\ \text{V} into 0 to 3.0\ \text{V}. The divider ratio is:
One ADC count corresponds to input-voltage change:
Engineering Interpretation
The quantization step is much smaller than many supply-voltage diagnostic thresholds, so ADC resolution is probably adequate. The actual accuracy still depends on resistor tolerance, reference accuracy, ADC offset, noise, input settling, protection leakage, and calibration.
Step 4: Anti-Alias Filter Check
For the vibration channel, choose a first-order RC low-pass filter with:
and:
The cutoff frequency is:
Substitute:
This cutoff is above the required 400\ \text{Hz} vibration bandwidth and below the 1000\ \text{Hz} Nyquist frequency for a 2000\ \text{Hz} sample rate.
Engineering Interpretation
A first-order filter provides limited attenuation near Nyquist. If high-frequency vibration or switching noise is significant, use a steeper analog filter, increase sampling rate, or prove that aliasing is acceptable for the measurement purpose.
Step 5: Data Rate
Assume each stored sample includes:
- 16-bit ADC value or speed value;
- 32-bit timestamp or sample counter;
- 16-bit status field.
Per sample:
Data rate:
| Channel | Rate | Bytes/sample | Data rate |
|---|---|---|---|
| Temperature | 10\ \text{Hz} | 8 | 80\ \text{B/s} |
| Supply voltage | 100\ \text{Hz} | 8 | 800\ \text{B/s} |
| Vibration | 2000\ \text{Hz} | 8 | 16000\ \text{B/s} |
| Speed update | 100\ \text{Hz} | 8 | 800\ \text{B/s} |
Total:
So the system produces about:
before packet framing, metadata, retries, and logs.
Step 6: Buffer Sizing
If the host link can pause for:
required buffer storage is:
Add 50\% margin:
A practical choice is:
Engineering Interpretation
The buffer fits in 96\ \text{kB} RAM, but the memory budget must also include stack, DMA descriptors, communication buffers, calibration tables, logs, and firmware update state. Buffer overflow policy must be defined before testing.
Step 7: Firmware Timing Budget
The high-rate vibration acquisition runs every:
Assume the acquisition interrupt and DMA service path takes:
The host packetization task runs every 10\ \text{ms} and takes:
The health monitor runs every 20\ \text{ms} and takes:
CPU utilization screen:
So the scheduled workload uses about:
before other firmware.
Engineering Interpretation
The utilization screen is comfortable, but timing still needs measurement. ADC trigger jitter, DMA contention, disabled interrupts, serial bursts, flash writes, and diagnostic logging can disturb acquisition even when average CPU load is low.
Step 8: Encoder Speed Calculation
Use a quadrature encoder with:
and 4\times decoding:
Counts per revolution:
At:
count frequency is:
Engineering Interpretation
The timer capture or counter hardware must handle about 410\ \text{kcounts/s} with margin. Do not service every edge with a long interrupt routine if the microcontroller cannot bound the latency. Hardware counters and periodic reads are often safer.
Step 9: Error Budget
For the supply-voltage channel, define a simplified worst-case error:
| Contributor | Error |
|---|---|
| Divider tolerance after calibration | 30\ \text{mV} |
| ADC reference error | 20\ \text{mV} |
| ADC noise and quantization | 10\ \text{mV} |
| Input leakage and protection | 15\ \text{mV} |
Worst-case sum:
Root-sum-square estimate:
Engineering Interpretation
If the brown-out diagnostic threshold has only 50\ \text{mV} margin, this measurement chain is not good enough without better calibration or filtering. If the threshold margin is 500\ \text{mV}, the channel may be adequate.
Step 10: Firmware Architecture
Use a bounded firmware structure:
- hardware timer triggers ADC conversions;
- DMA moves samples into a ring buffer;
- a short acquisition handler records timestamps and status flags;
- a packet task drains the buffer to the host link;
- a health monitor checks buffer fill, missed samples, ADC overruns, encoder errors, and watchdog conditions;
- calibration data are versioned and protected by integrity checks;
- fault states stop acquisition or mark data invalid rather than silently reporting stale values.
The host protocol should include sequence numbers. Missing sequence numbers are often more useful than a vague “communication failed” flag.
Step 11: Diagnostics and Fault Handling
Define diagnostic responses:
| Fault | Detection | Response |
|---|---|---|
| ADC overrun | hardware flag or missed DMA event | mark data invalid, increment counter, alert host. |
| Buffer near full | high-water mark | throttle low-priority data or assert backpressure. |
| Sensor saturation | ADC near rail for defined duration | flag sensor fault, preserve raw counts. |
| Thermocouple open | interface diagnostic or implausible value | report invalid temperature and safe status. |
| Encoder count jump | speed plausibility check | flag speed data and request inspection. |
| Host communication loss | timeout | continue bounded local buffer, then drop by defined policy. |
| Brown-out | voltage monitor and reset record | disable outputs, preserve reset cause, restart in safe mode. |
Fault handling should preserve evidence. Dropping data may be acceptable; silently reporting old data is usually not.
Step 12: Validation Plan
Validation should include:
- ADC scaling check at multiple known input voltages;
- frequency-response check for the vibration channel;
- anti-alias test with out-of-band signal;
- timestamp jitter measurement under communication load;
- buffer-overflow and host-pause test;
- encoder speed comparison against a reference tachometer;
- calibration load, corruption, and version-mismatch tests;
- brown-out and watchdog recovery tests;
- EMI or switching-noise exposure if the system operates near motors or power converters;
- long-duration logging with sequence-number audit.
Each validation result should state equipment used, operating conditions, firmware build, calibration version, sample count, and pass/fail criteria.
Project Deliverables
The final project report should include:
- measurement requirements and channel table;
- analog front-end and protection assumptions;
- sampling-rate justification;
- ADC scaling and error budget;
- anti-alias filter calculation;
- data-rate and buffer-size calculation;
- firmware timing budget;
- encoder count-rate check;
- diagnostics and safe fault responses;
- validation plan and representative results;
- known limitations and next design revision.
A strong data acquisition project does not end at “the ADC reads values.” It proves that the values represent the intended physical signals with known timing, bounded uncertainty, controlled failure behavior, and enough evidence for another engineer to trust the data.