Formula sheet

Digital Logic and Embedded Systems Formula Sheet

Digital logic formulas for Boolean laws, timing, I/O margins, buffers, bus bandwidth, sampling, quantization, latency, jitter, watchdogs, power, and reliability.

Branch: Computer Engineering
Content: Formula sheet
Updated: May 29, 2026
Revision: v1.0.8 · reviewed

This formula sheet collects first-pass relationships for digital logic, embedded timing, sampling, buses, power, and validation checks. Use it with clear definitions of voltage levels, clock domains, sample rates, firmware execution paths, protocol overhead, safety state, and measurement method.

Boolean Algebra

AND identity:

A\cdot 1=A

OR identity:

A+0=A

Complement:

A+\overline{A}=1

A\cdot\overline{A}=0

De Morgan laws:

\overline{AB}=\overline{A}+\overline{B}

\overline{A+B}=\overline{A}\cdot\overline{B}

XOR:

A\oplus B=A\overline{B}+\overline{A}B

Boolean simplification reduces gates, delay, power, and sometimes fault surface.

Logic Timing

Single-path propagation delay:

t_{pd,path}=\sum_i t_{pd,i}

Clock-period constraint:

T_{clk}\ge t_{clk\rightarrow Q}+t_{logic}+t_{setup}+t_{skew}+t_{margin}

Maximum clock frequency:

\displaystyle f_{max}=\frac{1}{T_{clk}}

Hold-time condition:

t_{clk\rightarrow Q,min}+t_{logic,min}\ge t_{hold}+t_{skew}

Check timing across process, voltage, temperature, loading, and clock-domain crossings.

Digital I/O Margins

High-level noise margin:

NM_H=V_{OH,min}-V_{IH,min}

Low-level noise margin:

NM_L=V_{IL,max}-V_{OL,max}

Pull-up current:

\displaystyle I_{PU}=\frac{V_{CC}-V_{in}}{R_{PU}}

RC rise-time estimate:

t_r\approx 2.2R_{PU}C_{line}

Debounce window:

t_{debounce}=N T_s

Digital I/O checks should include voltage family, input leakage, output drive, cable capacitance, EMC exposure, boot state, and fault tolerance.

Clock Domains and Synchronizers

Clock period:

\displaystyle T_{clk}=\frac{1}{f_{clk}}

Frequency ratio between two domains:

\displaystyle r_f=\frac{f_{fast}}{f_{slow}}

Two-flop synchronizer latency, approximate:

t_{sync}\approx 2T_{clk,dest}

Metastability MTBF screening form:

\displaystyle MTBF\approx \frac{e^{T_r/\tau}}{C f_{clk}f_{data}}

where $T_r$ is available resolution time and $\tau$ and $C$ are device-dependent parameters. Use vendor data and validation evidence for real safety or reliability claims.

Digital Throughput and Data Size

Bits per sample:

N_{bits,total}=N_{samples}N_{bits/sample}

Byte count:

\displaystyle N_{bytes}=\frac{N_{bits,total}}{8}

Raw data rate:

R_{raw}=f_s N_{bits/sample} N_{channels}

Required line data rate with overhead:

R_{line}=R_{raw}(1+\alpha_{overhead})

For a fixed line rate, the effective payload throughput is:

\displaystyle R_{payload,eff}=\frac{R_{line}}{1+\alpha_{overhead}}

where $\alpha_{overhead}$ represents framing, addressing, checksums, coding, idle time, and metadata.

Bus Bandwidth

Parallel bus raw bandwidth:

B_{raw}=w f_{clk}

where $w$ is bus width in bits.

Serial bus raw transfer time:

\displaystyle t_{tx}=\frac{N_{bits}}{R_b}

Effective throughput:

\displaystyle B_{eff}=\frac{N_{payload}}{t_{transaction}}

Bus utilization:

\displaystyle U=\frac{B_{required}}{B_{available}}

Use worst-case arbitration, retries, and interrupt handling for real-time systems, not only nominal bandwidth.

Buffers and Memory

Buffer fill time:

\displaystyle t_{fill}=\frac{B_{buffer}}{R_{in}-R_{out}}

when $R_{in}>R_{out}$ .

Required buffer size for a service gap:

B_{req}=R_{in}t_{gap}

Memory footprint:

M_{total}=M_{code}+M_{static}+M_{stack}+M_{heap}+M_{buffers}

Memory margin:

M_{margin}=M_{available}-M_{total}

Use bytes or bits consistently, and include alignment, DMA descriptors, protocol overhead, logging, bootloader, and worst-case stack depth.

Sampling

Sampling period:

\displaystyle T_s=\frac{1}{f_s}

Nyquist condition:

f_s>2B

Nyquist frequency:

\displaystyle f_N=\frac{f_s}{2}

Samples in a time window:

N=f_s T

Real systems need anti-alias filtering and margin because signal bandwidth and filter roll-off are finite.

Quantization

Ideal code count for an $N$ -bit ADC:

L=2^N

Least significant bit size:

\displaystyle LSB=\frac{V_{FS}}{2^N}

Maximum ideal quantization error:

\displaystyle e_q=\pm\frac{1}{2}LSB

Ideal quantization SNR for a full-scale sine:

SNR_q\approx 6.02N+1.76\ \text{dB}

Effective number of bits:

\displaystyle ENOB=\frac{SNR_{dB}-1.76}{6.02}

ADC accuracy also depends on reference, input settling, offset, gain error, noise, temperature, and layout.

Analog Input Filtering

RC low-pass cutoff:

\displaystyle f_c=\frac{1}{2\pi RC}

Capacitor impedance magnitude:

\displaystyle |X_C|=\frac{1}{2\pi fC}

Settling of a first-order input:

v(t)=V_f+(V_0-V_f)e^{-t/RC}

Input settling error:

e_s=e^{-t_s/RC}

Filtering should balance anti-aliasing, noise reduction, sensor bandwidth, and control-loop delay.

Latency Budget

Total embedded latency:

t_{total}=t_{sensor}+t_{filter}+t_{ADC}+t_{ISR}+t_{compute}+t_{bus}+t_{actuator}

Deadline margin:

M_t=t_{deadline}-t_{total,worst}

Control-loop sample-to-output delay:

t_{loop}=t_{sample}+t_{compute}+t_{update}

A positive average margin is not enough. Use worst-case or high-percentile latency for hard real-time behaviour.

Jitter

Peak-to-peak jitter:

J_{pp}=t_{max}-t_{min}

Root-mean-square jitter:

\displaystyle J_{rms}=\sqrt{\frac{1}{N}\sum_{i=1}^{N}(t_i-\bar{t})^2}

Relative sample-time error:

\displaystyle e_t=\frac{J}{T_s}

Jitter can reduce sampling accuracy, communication eye margin, and control stability.

Interrupt and CPU Utilization

CPU utilization from periodic tasks:

\displaystyle U_{CPU}=\sum_i \frac{C_i}{T_i}

where $C_i$ is worst-case execution time and $T_i$ is period.

Interrupt load:

U_{ISR}=\sum_i f_i C_i

Remaining CPU margin:

M_{CPU}=1-U_{CPU}

Use worst-case execution time, not typical execution time, for deadline checks.

Encoder and Count Rate

Counts per revolution:

N_c=N_{lines}m

where $m$ is decoding multiplier.

Measured speed:

\displaystyle \omega=\frac{2\pi \Delta counts}{N_c\Delta t}

Count frequency:

\displaystyle f_c=\frac{N_c\omega}{2\pi}

Check counter width, interrupt rate, debounce, input filtering, quadrature phase, and maximum speed.

Timers, Counters, and PWM

Timer tick period:

\displaystyle T_{tick}=\frac{Prescaler}{f_{clk}}

Counter rollover time:

t_{rollover}=2^N T_{tick}

PWM frequency:

\displaystyle f_{PWM}=\frac{f_{clk}}{Prescaler\cdot TOP}

PWM duty resolution:

\displaystyle \Delta D=\frac{1}{TOP}

Quantized pulse width:

t_{pulse}=Counts\cdot T_{tick}

Timer checks should include clock tolerance, interrupt latency, rollover handling, compare-update timing, actuator limits, and safe startup states.

PID Discrete Update

Discrete proportional term:

P_k=K_p e_k

Discrete integral update:

I_k=I_{k-1}+K_i T_s e_k

Discrete derivative estimate:

\displaystyle D_k=K_d\frac{e_k-e_{k-1}}{T_s}

Control output:

u_k=P_k+I_k+D_k

Real controllers need saturation handling, anti-windup, filtering, timing control, and safe output limits.

Power and Switching

Approximate CMOS dynamic power:

P_{dyn}=\alpha C V^2 f

where $\alpha$ is switching activity.

Energy per operation:

\displaystyle E_{op}=\frac{P}{f_{op}}

Regulator power loss, linear approximation:

P_{loss}=(V_{in}-V_{out})I_{out}

Battery runtime estimate:

\displaystyle t\approx \frac{C_{Ah}}{I_{avg}}

Power estimates should include sleep current, wake time, radio bursts, actuator loads, regulator efficiency, and temperature.

Error Budget

Root-sum-square independent error:

e_{RSS}=\sqrt{\sum_i e_i^2}

Worst-case bounded error:

e_{WC}=\sum_i |e_i|

Relative error:

\displaystyle e_{rel}=\frac{|x_{measured}-x_{reference}|}{|x_{reference}|}

Allocate error across sensor, analog conditioning, ADC, reference, calibration, computation, timing, communication, and actuator response.

Reliability and Watchdog Checks

Reliability for constant failure rate:

R(t)=e^{-\lambda t}

Mean time between failures:

\displaystyle MTBF=\frac{1}{\lambda}

Watchdog timeout condition:

t_{normal,max}<t_{watchdog}<t_{unsafe}

Diagnostic coverage:

\displaystyle DC=\frac{\lambda_{detected}}{\lambda_{total}}

Watchdog recovery should be validated with stuck-loop, interrupt-lockout, brown-out, bus-lockup, and memory-corruption tests.

Validation Metrics

Test pass rate:

\displaystyle P_{pass}=\frac{N_{pass}}{N_{tests}}

Bit error rate:

\displaystyle BER=\frac{N_{errors}}{N_{bits}}

Packet loss ratio:

\displaystyle PLR=\frac{N_{lost}}{N_{sent}}

Mean measured latency:

\displaystyle \bar{t}=\frac{1}{N}\sum_i t_i

Validation should include nominal operation, boundary values, fault injection, power cycling, EMI exposure, timing stress, communication errors, and safe-state verification.

REF

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