Glossary term
XOR Gate
A digital logic gate whose output is true when inputs differ, commonly used for parity, adders, and bitwise comparison.
Definition
deviceAn XOR gate is a digital logic gate that outputs logic 1 when its inputs differ and logic 0 when they are the same.
The exclusive-OR operation is central to parity checks, binary addition, comparators, toggling logic, phase detection, checksums, simple encryption operations, and error-detection circuits. In hardware, XOR behaviour may be implemented with transistor logic, standard-cell gates, programmable logic, or firmware expressions.
An XOR gate implements the exclusive-OR Boolean operation. For two inputs, the output is 1 when exactly one input is 1 and the other is 0. The output is 0 when both inputs are 0 or both inputs are 1. This makes XOR a “difference” detector for binary states.
For two inputs:
| A | B | A XOR B |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Engineering use
XOR gates are used in half adders and full adders, parity generation, parity checking, cyclic redundancy checks, address decoding, toggle flip-flop structures, pseudo-random sequences, phase detectors, and bitwise software operations. Multi-input XOR is often interpreted as odd parity: the output is 1 when an odd number of inputs are 1.
In hardware design, propagation delay, input threshold, fan-out, hazard behaviour, power consumption, and process-voltage-temperature variation affect the gate. In high-speed systems, XOR delay and routing skew can be part of a timing closure problem, especially in adders, serializers, clock-data recovery, and error-detection paths.
Common mistakes
A common mistake is confusing XOR with inclusive OR. Inclusive OR is true when either input or both inputs are true; XOR is false when both inputs are true. Another mistake is extending the two-input definition to many inputs without stating whether the intended function is exactly-one logic or odd-parity logic. A strong digital design review states the truth table, voltage logic family, timing budget, fan-out, reset or initialization assumptions, and how glitches are handled.