Exercise set

Digital Logic and Timing Analysis Exercises

Worked computer engineering exercises for digital logic and embedded timing, covering Boolean simplification, propagation delay, setup and hold checks, synchronizers, bus throughput, buffers, sampling, quantization, jitter, interrupt load, timers, PWM, and release evidence.

Branch: Computer Engineering
Content: Exercise set
Updated: Jun 20, 2026
Revision: v1.0.0 · reviewed

These exercises practise digital logic and embedded timing analysis as engineering evidence. They cover Boolean simplification, propagation delay, setup and hold timing, clock-domain crossing screens, bus throughput, buffer sizing, sampling, quantization, jitter, interrupt load, timer resolution, PWM resolution, and release checks.

The goal is not only to obtain a number. The goal is to decide whether a digital function can meet its logic, timing, measurement, communication, and fault-response requirements on real hardware.

Assume simplified screening models unless an exercise states otherwise. Real systems should also check process-voltage-temperature corners, clock tolerance, board delay, signal integrity, reset behavior, firmware scheduling, electromagnetic interference, diagnostics, and validation records.

How to Use These Exercises

For each exercise, define:

the logic path, clock domain, bus, measurement, or firmware task being assessed;
the required timing, accuracy, throughput, or safe-state behavior;
the margin between requirement and estimated performance;
the physical assumptions behind the estimate;
the evidence needed before release.

The common mistake is treating digital logic as ideal. A Boolean expression can be correct while the implemented circuit fails because of propagation delay, metastability, bus contention, interrupt overload, weak pull-ups, noisy inputs, or insufficient validation.

Exercise 1: Boolean Simplification

A combinational output is defined as:

Y=A\overline{B}+AB

Simplify the expression.

Solution

Factor out $A$ :

Y=A(\overline{B}+B)

Since:

\overline{B}+B=1

the output becomes:

Y=A

Engineering Comment

The simplified logic needs fewer gates and usually less delay, area, and switching power. The review should still check whether the original expression came from a safety requirement, diagnostic condition, or deliberately redundant implementation.

Exercise 2: Propagation Delay of a Logic Path

A combinational path contains three gates with propagation delays:

t_1=1.8\ \text{ns}

t_2=2.4\ \text{ns}

t_3=1.1\ \text{ns}

Estimate the path delay.

Solution

For a simple serial path:

t_{pd,path}=t_1+t_2+t_3

Substitute:

t_{pd,path}=1.8+2.4+1.1=5.3\ \text{ns}

Engineering Comment

This is a nominal path estimate. Real timing must include routing delay, loading, input slew, output drive, temperature, voltage, and the timing model used by the implementation tool.

Exercise 3: Maximum Clock Frequency

A synchronous path has:

t_{clk\rightarrow Q}=0.55\ \text{ns}

t_{logic}=6.40\ \text{ns}

t_{setup}=0.35\ \text{ns}

t_{skew}=0.20\ \text{ns}

t_{margin}=0.50\ \text{ns}

Compute the minimum clock period and maximum clock frequency.

Solution

The minimum period is:

T_{clk,min}=t_{clk\rightarrow Q}+t_{logic}+t_{setup}+t_{skew}+t_{margin}

Substitute:

T_{clk,min}=0.55+6.40+0.35+0.20+0.50=8.00\ \text{ns}

Therefore:

\displaystyle f_{max}=\frac{1}{8.00\times10^{-9}}=125\times10^6\ \text{Hz}

So:

f_{max}=125\ \text{MHz}

Engineering Comment

This path may support 125 MHz under the assumed conditions. A release decision should still check worst-case timing reports, unconstrained paths, clock uncertainty, generated clocks, I/O timing, and whether this path is actually the critical path.

Exercise 4: Setup Slack

A register-to-register path must run with:

T_{clk}=10.0\ \text{ns}

The data path and timing terms are:

t_{clk\rightarrow Q}=0.60\ \text{ns}

t_{logic}=7.50\ \text{ns}

t_{setup}=0.30\ \text{ns}

t_{uncertainty}=0.40\ \text{ns}

Compute setup slack.

Solution

Setup slack is:

S_{setup}=T_{clk}-t_{clk\rightarrow Q}-t_{logic}-t_{setup}-t_{uncertainty}

Substitute:

S_{setup}=10.0-0.60-7.50-0.30-0.40=1.20\ \text{ns}

Engineering Comment

The path has positive setup slack. The 1.20 ns margin is useful, but it should not hide missing constraints, false-path errors, or measurements taken at only one voltage and temperature condition.

Exercise 5: Hold Margin

A hold check has:

t_{clk\rightarrow Q,min}=0.18\ \text{ns}

t_{logic,min}=0.24\ \text{ns}

t_{hold}=0.20\ \text{ns}

Clock skew reduces the available hold margin by:

t_{skew}=0.12\ \text{ns}

Compute hold margin:

S_{hold}=t_{clk\rightarrow Q,min}+t_{logic,min}-t_{hold}-t_{skew}

Solution

Substitute:

S_{hold}=0.18+0.24-0.20-0.12=0.10\ \text{ns}

Engineering Comment

The hold margin is positive but small. Lowering the clock frequency does not fix hold violations. Hold review needs minimum-delay analysis, clock-tree behavior, routing, constraints, and any clock-domain crossing assumptions.

Exercise 6: Synchronizer Latency

An asynchronous status signal is sampled through a two-flop synchronizer in a destination clock domain running at:

f_{dest}=50\ \text{MHz}

Estimate synchronizer latency using:

t_{sync}\approx 2T_{clk,dest}

Solution

The destination clock period is:

\displaystyle T_{clk,dest}=\frac{1}{50\times10^6}=20\ \text{ns}

Then:

t_{sync}\approx 2(20)=40\ \text{ns}

Engineering Comment

The two-flop synchronizer reduces metastability risk for a single-bit level signal, but it is not a complete solution for multi-bit data, pulses shorter than the destination clock, reset release, or safety-critical event capture.

Exercise 7: Effective Bus Throughput

A serial bus has line rate:

R_{line}=12\ \text{Mbit/s}

Protocol overhead is:

\alpha_{overhead}=0.25

Estimate effective payload throughput:

\displaystyle R_{payload,eff}=\frac{R_{line}}{1+\alpha_{overhead}}

Solution

Substitute:

\displaystyle R_{payload,eff}=\frac{12}{1.25}=9.6\ \text{Mbit/s}

Engineering Comment

This estimate still ignores arbitration, retries, idle time, interrupt service, DMA setup, and driver buffering. For real-time traffic, worst-case transaction time may be more important than average throughput.

Exercise 8: Buffer Size for a Service Gap

A sensor stream produces:

R_{in}=80\ \text{kB/s}

The processor can be busy for a maximum service gap of:

t_{gap}=120\ \text{ms}

Estimate the minimum buffer size:

B_{req}=R_{in}t_{gap}

Solution

Convert:

t_{gap}=0.120\ \text{s}

Compute:

B_{req}=80(0.120)=9.6\ \text{kB}

Engineering Comment

The buffer should be larger than 9.6 kB after accounting for framing, burstiness, interrupt latency, DMA descriptors, watermark policy, and diagnostic logging. Increasing buffer size does not solve a sustained overload where average service rate is too low.

Exercise 9: Sampling and Nyquist Frequency

An embedded system samples a vibration signal at:

f_s=4.0\ \text{kHz}

Compute the Nyquist frequency and state whether a 2.6 kHz component can be represented without aliasing in the ideal sampling model.

Solution

Nyquist frequency is:

\displaystyle f_N=\frac{f_s}{2}=\frac{4.0}{2}=2.0\ \text{kHz}

A 2.6 kHz component is above 2.0 kHz, so it violates the ideal Nyquist limit.

Engineering Comment

The input needs a higher sample rate, an anti-alias filter that attenuates 2.6 kHz sufficiently, or a revised measurement requirement. Real anti-alias filters need transition-band margin, not only the mathematical cutoff.

Exercise 10: ADC Quantization Step

An ADC has:

N=12\ \text{bits}

and full-scale range:

V_{FS}=3.3\ \text{V}

Compute the ideal least significant bit size:

\displaystyle LSB=\frac{V_{FS}}{2^N}

Solution

The number of codes is:

2^{12}=4096

Therefore:

\displaystyle LSB=\frac{3.3}{4096}=0.0008057\ \text{V}

So:

LSB\approx 0.806\ \text{mV}

Engineering Comment

The ideal quantization step is only one part of measurement quality. Reference accuracy, sensor error, input impedance, settling, grounding, temperature drift, noise, calibration, and firmware scaling may dominate the error budget.

Exercise 11: Jitter as a Fraction of Sampling Period

A control loop samples at:

f_s=1.0\ \text{kHz}

Measured peak timing jitter is:

J=18\ \mu\text{s}

Compute relative sample-time error:

\displaystyle e_t=\frac{J}{T_s}

Solution

Sampling period:

\displaystyle T_s=\frac{1}{1000}=1.0\ \text{ms}

Convert:

J=0.018\ \text{ms}

Then:

\displaystyle e_t=\frac{0.018}{1.0}=0.018

Therefore:

e_t=1.8\%

Engineering Comment

Whether 1.8% is acceptable depends on control bandwidth, phase margin, sensor dynamics, actuator delay, and fault response. Jitter should be measured under realistic interrupt, communication, and logging load.

Exercise 12: Interrupt CPU Load

Three periodic interrupts have the following worst-case execution times:

Interrupt	Frequency	Execution time
Timer control	1.0 kHz	18 us
Encoder capture	4.0 kHz	5 us
Communication receive	800 Hz	12 us

Estimate total interrupt CPU utilization:

U_{ISR}=\sum_i f_i C_i

Solution

Timer control:

U_1=(1000)(18\times10^{-6})=0.018

Encoder capture:

U_2=(4000)(5\times10^{-6})=0.020

Communication receive:

U_3=(800)(12\times10^{-6})=0.0096

Total:

U_{ISR}=0.018+0.020+0.0096=0.0476

Therefore:

U_{ISR}=4.76\%

Engineering Comment

This interrupt load is moderate, but the calculation does not prove deadline safety. The design must also check priority inversion, disabled-interrupt intervals, nested interrupts, cache effects, bus stalls, shared data, stack margin, and worst-case burst behavior.

Exercise 13: Timer Resolution and Rollover

A 16-bit timer runs from a clock:

f_{clk}=48\ \text{MHz}

with prescaler:

Prescaler=48

Compute timer tick period and rollover time:

\displaystyle T_{tick}=\frac{Prescaler}{f_{clk}}

t_{rollover}=2^{16}T_{tick}

Solution

Tick period:

\displaystyle T_{tick}=\frac{48}{48\times10^6}=1.0\ \mu\text{s}

Rollover time:

t_{rollover}=65536(1.0\ \mu\text{s})=65.536\ \text{ms}

Engineering Comment

A 1 us tick gives useful timestamp resolution, but a 65.536 ms rollover must be handled correctly. Firmware should test rollover arithmetic, capture latency, interrupt delay, and clock tolerance.

Exercise 14: PWM Duty Resolution

A PWM timer uses:

TOP=999

so it has 1000 discrete duty counts from 0 to 999. Estimate duty-cycle resolution:

\displaystyle \Delta D=\frac{1}{1000}

Solution

Compute:

\Delta D=0.001

Therefore:

\Delta D=0.1\%

Engineering Comment

Duty resolution is not the same as actuator resolution. Output driver dead time, switching frequency, motor inductance, load dynamics, supply ripple, timer update timing, and safe startup state can dominate actual behavior.

Exercise 15: Release Evidence for a Timing Change

A firmware revision increases the control-loop computation time from:

C_{old}=210\ \mu\text{s}

to:

C_{new}=265\ \mu\text{s}

The loop period is:

T=1.0\ \text{ms}

The existing timing budget reserved:

M_{old}=180\ \mu\text{s}

of margin. Determine the new margin.

Solution

The computation-time increase is:

\Delta C=C_{new}-C_{old}=265-210=55\ \mu\text{s}

The new margin is:

M_{new}=M_{old}-\Delta C=180-55=125\ \mu\text{s}

Engineering Comment

The margin remains positive, but release still needs trace evidence under representative load. A timing change should update worst-case execution measurement, interrupt-latency records, stack margin, watchdog assumptions, control-loop validation, and rollback criteria.

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