Exercise set

PCB Design, Power Integrity, and Signal Integrity Exercises

Worked electronic engineering exercises for PCB design, power integrity, and signal integrity covering transmission-line screening, PDN target impedance, decoupling resonance, via inductance, voltage drop, loop area, trace heating, junction temperature, skew, measurement error, and release evidence.

Branch: Electronic Engineering
Content: Exercise set
Updated: Jun 20, 2026
Revision: v1.1.0 · reviewed

These exercises practise PCB design as a physical engineering problem. They cover transmission-line screening, PDN target impedance, decoupling resonance, via inductance, trace voltage drop, loop area, copper temperature, junction temperature, differential skew, measurement setup, and release evidence.

The goal is not only to calculate a board-level number. The goal is to decide whether stackup, copper geometry, return path, decoupling, thermal path, manufacturing data, and validation measurements support the intended circuit behavior.

Assume simplified first-pass models unless an exercise states otherwise. Real PCB design should also check field-solver impedance, material tolerance, copper roughness, via geometry, package parasitics, connector models, component derating, EMC test setup, thermal boundary conditions, assembly variation, and revision control.

How to Use These Exercises

For each calculation, define:

the net, rail, loop, or component being assessed;
the frequency or edge-rate range that makes layout important;
the reference plane and return path;
the manufacturing or measurement tolerance behind the number;
the validation action needed before release.

The common mistake is treating the PCB as ideal connectivity. A PCB is an electromagnetic, thermal, mechanical, and manufacturing structure.

For each result, state whether it supports stackup approval, routing constraint, PDN margin, decoupling placement, thermal derating, measurement acceptance, or board-release hold. A PCB calculation is release-relevant only when the physical geometry, manufacturing data, test setup, and board revision are identified.

Exercise 1: Transmission-Line Screening from Rise Time

A digital signal has rise time:

t_r=900\ \text{ps}

The trace has one-way propagation delay:

t_{pd}=180\ \text{ps}

Use the first-pass screening rule:

\displaystyle t_{pd}>\frac{t_r}{6}

Decide whether transmission-line behavior should be reviewed.

Solution

Compute the threshold:

\displaystyle \frac{t_r}{6}=\frac{900}{6}=150\ \text{ps}

Compare:

180\ \text{ps}>150\ \text{ps}

The interconnect should be reviewed as a transmission line.

Engineering Comment

The result does not automatically require termination, but it does require layout review. Check controlled impedance, return path continuity, source impedance, receiver threshold, overshoot, undershoot, via transitions, connector discontinuities, and measurement bandwidth.

Exercise 2: Trace Length from Propagation Delay

A microstrip-like trace is estimated to have delay:

d=160\ \text{ps/in}

The signal rise time is:

t_r=1.2\ \text{ns}

Using the same screening rule, estimate the trace length above which transmission-line effects should be reviewed.

Solution

Threshold delay is:

\displaystyle t_{limit}=\frac{t_r}{6}=\frac{1.2\ \text{ns}}{6}=0.20\ \text{ns}

Convert to picoseconds:

0.20\ \text{ns}=200\ \text{ps}

Length threshold is:

\displaystyle L=\frac{t_{limit}}{d}=\frac{200}{160}=1.25\ \text{in}

Traces longer than about 1.25 inches should be reviewed for transmission-line behavior.

Engineering Comment

This is a screening threshold, not a routing law. A shorter trace can still cause trouble if it crosses a reference-plane gap, drives a high-impedance receiver, enters a connector, or belongs to a low-noise analog or clock path.

Exercise 3: PDN Target Impedance

A processor rail allows maximum transient droop:

\Delta V_{max}=60\ \text{mV}

The expected load step is:

\Delta I=1.5\ \text{A}

Estimate the target power-distribution-network impedance:

\displaystyle Z_{target}=\frac{\Delta V_{max}}{\Delta I}

Solution

Substitute:

\displaystyle Z_{target}=\frac{60\ \text{mV}}{1.5\ \text{A}}

Convert:

60\ \text{mV}=0.060\ \text{V}

Therefore:

\displaystyle Z_{target}=\frac{0.060}{1.5}=0.040\ \Omega

The target impedance is:

Z_{target}=40\ \text{m}\Omega

Engineering Comment

The design task is not simply adding capacitors. The PDN must stay below this impedance over the relevant load spectrum, including regulator response, plane inductance, capacitor ESL, package inductance, mounting geometry, and anti-resonance.

Exercise 4: Decoupling Capacitor Resonant Frequency

A decoupling capacitor has capacitance:

C=100\ \text{nF}

Its effective loop inductance including mounting and vias is:

L=0.8\ \text{nH}

Estimate the series resonant frequency:

\displaystyle f_0=\frac{1}{2\pi\sqrt{LC}}

Solution

Convert:

C=100\times10^{-9}\ \text{F}

L=0.8\times10^{-9}\ \text{H}

Compute:

\displaystyle f_0=\frac{1}{2\pi\sqrt{(0.8\times10^{-9})(100\times10^{-9})}}

f_0=17.8\ \text{MHz}

Engineering Comment

This frequency is only the local resonance estimate. The useful decoupling behavior also depends on ESR, plane spreading inductance, package inductance, capacitor array interactions, placement, vias, and the load-current frequency content.

Exercise 5: Via Inductance Transient Droop

A power pin is supplied through a via path with effective inductance:

L=1.2\ \text{nH}

The load current changes by:

\Delta I=0.8\ \text{A}

in:

\Delta t=2.0\ \text{ns}

Estimate inductive voltage droop:

\displaystyle V_L=L\frac{\Delta I}{\Delta t}

Solution

Compute current slew rate:

\displaystyle \frac{\Delta I}{\Delta t}=\frac{0.8}{2.0\times10^{-9}}=4.0\times10^8\ \text{A/s}

Then:

V_L=(1.2\times10^{-9})(4.0\times10^8)=0.48\ \text{V}

Engineering Comment

The result shows why mounting inductance can dominate fast supply events. A 0.48 V transient is unacceptable for many rails. The response is shorter current loops, local decoupling, multiple vias, better plane coupling, package-aware layout, or reduced edge current where possible.

Exercise 6: DC Trace Voltage Drop

A power trace carries:

I=1.8\ \text{A}

Its estimated resistance from regulator to load is:

R=38\ \text{m}\Omega

Calculate voltage drop and power dissipated in the trace.

Solution

Voltage drop:

V_{drop}=IR

V_{drop}=1.8(0.038)=0.0684\ \text{V}

Power:

P=I^2R

P=(1.8)^2(0.038)=0.123\ \text{W}

Engineering Comment

The 68.4 mV drop may be acceptable or unacceptable depending on rail tolerance and load transient margin. The 0.123 W heat source also matters if the trace is narrow, buried, near hot components, or part of a dense board region.

Exercise 7: Loop Area Reduction

A switching-regulator input loop originally has approximate area:

A_1=180\ \text{mm}^2

After placement revision, the loop area is:

A_2=45\ \text{mm}^2

Calculate the percentage reduction in loop area.

Solution

Reduction is:

\displaystyle R=\frac{A_1-A_2}{A_1}\times100

Substitute:

\displaystyle R=\frac{180-45}{180}\times100=75\%

Engineering Comment

Reducing high di/dt loop area by 75 percent is usually valuable for EMI and switch-node coupling. The layout review should still check capacitor placement, return via placement, switch-node copper, gate-drive loop, current-sense routing, and thermal spreading.

Exercise 8: Junction Temperature Check

A regulator dissipates:

P_D=0.85\ \text{W}

The board-level thermal resistance estimate is:

\theta_{JA}=48^\circ\text{C/W}

Ambient temperature is:

T_A=55^\circ\text{C}

Estimate junction temperature:

T_J=T_A+P_D\theta_{JA}

Solution

Compute rise:

\Delta T=P_D\theta_{JA}=0.85(48)=40.8^\circ\text{C}

Then:

T_J=55+40.8=95.8^\circ\text{C}

Engineering Comment

The estimated junction temperature is about 96 degrees Celsius. This should be checked against datasheet limits, derating policy, neighboring heat sources, copper area, airflow, enclosure contact, duty cycle, and thermal measurements on real hardware.

Exercise 9: Differential Pair Skew

A differential pair has length mismatch:

\Delta L=4.5\ \text{mm}

The propagation delay is:

d=6.0\ \text{ps/mm}

Calculate the skew introduced by the mismatch.

Solution

Skew is:

t_{skew}=\Delta Ld

t_{skew}=4.5(6.0)=27\ \text{ps}

Engineering Comment

Whether 27 ps matters depends on interface speed, jitter budget, receiver tolerance, encoding, equalization, and channel margin. Length matching should not be applied blindly; it should protect a timing or eye-margin requirement.

Exercise 10: Probe Ground Lead Inductance Error

An oscilloscope probe ground lead has estimated inductance:

L_g=20\ \text{nH}

The measured node has transient current coupled into the probe loop with slew rate:

\displaystyle \frac{di}{dt}=0.05\ \text{A/ns}

Estimate the induced voltage:

\displaystyle V=L_g\frac{di}{dt}

Solution

Convert slew rate:

0.05\ \text{A/ns}=0.05\times10^9\ \text{A/s}=5.0\times10^7\ \text{A/s}

Compute:

V=(20\times10^{-9})(5.0\times10^7)=1.0\ \text{V}

Engineering Comment

A long probe ground lead can create a measurement artifact large enough to dominate the signal. High-speed and low-noise board measurements should define probe type, ground spring or coaxial connection, bandwidth limit, loading, and measurement location.

Exercise 11: RC Edge-Rate Filtering

A damping resistor and input capacitance form an approximate RC time constant. The resistor is:

R=33\ \Omega

The effective capacitance is:

C=8\ \text{pF}

Estimate the time constant:

\tau=RC

and the approximate 10-to-90 percent rise-time contribution:

t_r\approx2.2\tau

Solution

Time constant:

\tau=(33)(8\times10^{-12})=264\times10^{-12}\ \text{s}

\tau=264\ \text{ps}

Rise-time contribution:

t_r\approx2.2(264)=581\ \text{ps}

Engineering Comment

Series damping can reduce ringing and emissions, but it consumes timing margin. The resistor value should be checked against source impedance, receiver threshold, trace impedance, setup and hold timing, and EMC goals.

Exercise 12: Bring-Up Release Evidence Completion

A PCB release checklist requires ten evidence items:

schematic and layout revision match;
stackup and impedance notes released;
fabrication and assembly data archived;
power-rail startup captures recorded;
load-transient measurements recorded;
thermal image under worst-case duty;
clock or data-bus margin checked;
EMC pre-scan or risk review complete;
manufacturing deviations dispositioned;
firmware and test-fixture versions recorded.

At release review, eight items are complete.

Calculate the completion percentage and decide whether release is acceptable if all ten items are mandatory.

Solution

Completion fraction:

\displaystyle f=\frac{8}{10}=0.80

Convert:

f=80\%

Because all ten items are mandatory, the board should not be released.

Engineering Comment

Missing release evidence can invalidate a passing prototype. A board revision is only controlled when schematic, layout, BOM, fab data, assembly state, firmware, measurement setup, and validation records describe the same physical article.

Review Checklist

When reviewing PCB power integrity and signal integrity evidence, ask:

Which traces need transmission-line review because of rise time, not just data rate?
Does every fast or high-current signal have a continuous return path?
Is PDN impedance compared against load transient requirements over frequency?
Are decoupling capacitors placed and via-connected for the current they must supply?
Are loop areas, cable currents, plane splits, and connector filters reviewed for EMI?
Are thermal estimates validated with realistic copper, airflow, enclosure, and duty cycle?
Are oscilloscope and probing methods documented well enough to trust the waveform?
Are stackup, dielectric, copper weight, impedance notes, via structures, and assembly deviations controlled in the released fabrication data?
Are measurement artifacts, probe loading, fixture effects, cable configuration, and firmware state separated from true board behavior?
Do manufacturing notes, stackup, impedance requirements, BOM, firmware, and validation records describe the same board revision?

Good PCB design makes physical assumptions measurable. Copper geometry, dielectric material, return paths, decoupling, thermal paths, manufacturing data, and test records are part of the circuit.

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