Project
ECG Signal Acquisition Verification Project
ECG acquisition verification with SNR, resolution, CMRR, leakage current, latency, data integrity, risk controls, test evidence, and release decision.
This project verifies an ECG signal acquisition chain for a biomedical monitoring device. The goal is to produce an engineering verification package: intended measurement boundary, requirements, test methods, SNR calculation, ADC resolution check, common-mode rejection check, leakage-current evidence, latency budget, data-integrity controls, risk links, and release decision.
The project is not clinical advice and not a complete regulatory submission. It focuses on the engineering evidence needed to decide whether the acquisition chain is credible for its stated intended use.
Project Objective
Verify a three-electrode ECG acquisition subsystem intended to support heart-rate trending and waveform display in a monitored environment. The final deliverable should answer:
- Is the input signal large enough relative to noise over the stated bandwidth?
- Does ADC resolution preserve clinically meaningful waveform features for the intended display and heart-rate algorithm?
- Does common-mode rejection reduce mains interference to an acceptable input-referred level?
- Is patient leakage current within the engineering limit used for the verification plan?
- Does acquisition and processing latency satisfy the system response requirement?
- Which tests, records, and risk controls must be complete before release?
The deliverable should be a verification report with traceability from requirement to test result, not only a set of bench measurements.
Baseline Requirements
Use the following simplified requirements for the project.
| Requirement | Acceptance criterion |
|---|---|
| Input ECG signal range | 0.5 to 5.0\ \text{mV}_{RMS} |
| Display and heart-rate bandwidth | 0.5 to 40\ \text{Hz} |
| Minimum input-referred SNR for nominal test signal | 30\ \text{dB} |
| Sampling rate | at least 500\ \text{samples/s} |
| ADC resolution at input | at most 5\ \mu\text{V/count} |
| Mains residual after CMRR | at most 20\ \mu\text{V}_{RMS} input referred |
| Patient leakage current engineering limit | at most 10\ \mu\text{A} |
| Acquisition-to-display latency | less than 250\ \text{ms} |
| Data dropouts during verification record | none longer than 100\ \text{ms} |
These requirements are simplified for an engineering exercise. Real medical-device work must use the applicable standards, intended use, patient population, risk management file, usability evidence, electrical safety requirements, EMC tests, software lifecycle evidence, cybersecurity controls, and clinical validation plan.
System Under Test
The acquisition chain includes:
- electrodes and lead wires;
- input protection and patient isolation boundary;
- instrumentation amplifier and driven reference circuit;
- analog high-pass and low-pass filtering;
- analog-to-digital conversion;
- firmware timestamping and packetization;
- digital filtering and heart-rate feature extraction;
- display and data logging.
The verification boundary starts at the electrode input connector and ends at the timestamped waveform record and displayed signal-quality status.
Configuration Control
The verification run is valid only for the documented configuration. Record hardware revision, analog front-end component values, isolation barrier version, electrode and lead-wire type, firmware commit, filter coefficients, sample rate, display software, alarm thresholds and any service-mode settings used during the test.
If a later change alters gain, bandwidth, input protection, isolation, digital filtering, timestamping or signal-quality logic, the affected requirements must be re-evaluated. Reusing an old clean waveform after a firmware or accessory change is not a defensible release argument.
Evidence Boundary
Separate engineering verification from clinical validation. This project verifies that the acquisition chain can preserve a calibrated ECG-like signal under specified bench conditions. It does not prove diagnostic performance, population coverage, alarm clinical effectiveness or usability under real patient motion.
Step 1: SNR Verification
The bench simulator provides:
in the verification bandwidth. Measured input-referred noise is:
Assuming equal impedance, voltage SNR in decibels is:
Convert the signal:
Compute:
Engineering Comment
The SNR requirement passes for the nominal simulator condition because 34.0\ \text{dB} exceeds the 30\ \text{dB} criterion. The report must still state electrode condition, bandwidth, cable setup, filter state, and whether the noise is input-referred or output-measured.
Electrode-Impedance Condition
A nominal simulator with low source impedance is not enough. Add a second run with electrode imbalance, for example:
The acceptance question is whether the input-referred noise and mains residual remain inside limits when the common-mode signal is partially converted into differential error by impedance mismatch.
Motion-Artefact Screen
For a controlled engineering screen, inject a low-frequency baseline disturbance and confirm that the system does not convert artefact into a stable heart-rate output without signal-quality warning. The pass condition should include both waveform evidence and status-bit evidence.
Step 2: ADC Resolution Check
The ADC has:
full-scale input range:
and analog front-end gain:
Total ADC span:
ADC count levels:
Output-side voltage per count:
Input-referred voltage per count:
Therefore:
Engineering Comment
The ADC resolution requirement passes because 2.5\ \mu\text{V/count} is below the 5\ \mu\text{V/count} limit. Resolution alone does not prove accuracy; offset, gain error, drift, filtering, saturation recovery, electrode artefact, and timestamp integrity remain separate checks.
Dynamic Range and Headroom
Check that expected electrode offset and motion artefact do not force the front end into saturation before the ECG component reaches the ADC. A useful headroom record lists input offset, gain, supply rails, protection clamp threshold and measured recovery time after a step disturbance.
If the analog chain clips, later digital filtering can make the displayed waveform appear smoother while the underlying information is already lost.
Step 3: Common-Mode Rejection Check
The common-mode mains test applies:
The measured common-mode rejection ratio is:
Convert CMRR from decibels to ratio:
Input-referred residual:
Engineering Comment
The common-mode residual passes the 20\ \mu\text{V}_{RMS} input-referred criterion. The test should be repeated with realistic electrode impedance imbalance because high CMRR on a shorted input does not prove performance with skin-electrode mismatch and moving leads.
Mains-Frequency Coverage
Run the CMRR test at the site-relevant mains frequency and its configured notch-filter condition. If the device can be used in both 50\ \text{Hz} and 60\ \text{Hz} regions, the report should not treat one frequency as evidence for the other unless the filter and analog response are explicitly equivalent.
Step 4: Leakage-Current Evidence
Measured patient leakage current under the verification condition is:
Engineering limit:
Margin:
Percentage of limit:
or:
Engineering Comment
The leakage-current check passes for this simplified project. The report must state test configuration, supply mode, applied parts, environmental condition, accessory set, and whether the measurement represents normal condition or a fault condition.
Accessory and Isolation Traceability
Leakage-current evidence is weak unless it identifies the patient cable, electrode type, isolation barrier, enclosure state and power configuration. If accessories are interchangeable, the release package should state which combinations are covered and which combinations require separate evidence.
Do not use an electronics-only bench test as evidence for the patient-applied system if the cable, connector, shield or isolation path differs from the released configuration.
Step 5: Latency Budget
Measured or allocated latency values are:
| Element | Latency |
|---|---|
| analog front-end settling and anti-alias filtering | 8\ \text{ms} |
| ADC frame and timestamping | 10\ \text{ms} |
| digital filter group delay | 55\ \text{ms} |
| heart-rate feature extraction | 30\ \text{ms} |
| packet transfer and display update | 80\ \text{ms} |
Total latency:
Margin against the 250\ \text{ms} requirement:
Engineering Comment
The latency budget passes. The project should verify not only average latency but also jitter, buffer overrun behavior, lost packets, timestamp monotonicity, and recovery after lead-off or motion artefact.
Timestamp and Data-Integrity Test
Run a continuous record long enough to expose buffer rollover, display refresh and packet recovery behavior. The raw data should include sequence counters or timestamps. A practical dropout metric is:
The test passes only if the waveform record, displayed status and stored log agree about missing samples. Silent interpolation may be acceptable for display smoothing, but it should not hide acquisition loss from the engineering record.
Alarm and Signal-Quality Coupling
If heart-rate output is displayed while lead-off, saturation, excessive noise or stale data are present, the project must verify how the system marks that output. Release evidence should show the value, timestamp and signal-quality state together, not as separate screenshots.
Step 6: Verification Matrix
| Requirement | Evidence | Acceptance decision |
|---|---|---|
| SNR at nominal simulator signal | bench waveform record with input-referred noise | pass if at least 30\ \text{dB} |
| ADC resolution | calculation from range, bits, and gain plus code histogram | pass if at most 5\ \mu\text{V/count} |
| CMRR | common-mode injection with electrode imbalance cases | pass if residual at most 20\ \mu\text{V}_{RMS} |
| leakage current | electrical safety measurement record | pass if at most 10\ \mu\text{A} for this plan |
| latency | timestamped acquisition-to-display test | pass if less than 250\ \text{ms} |
| data integrity | continuous record with sequence counters | pass if no dropout longer than 100\ \text{ms} |
| risk controls | traceability to lead-off, saturation, and noise alarms | pass if hazards have verified controls |
Each test record should include hardware revision, firmware version, electrode/accessory setup, simulator model, calibration status, environmental condition, sample rate, filter configuration, raw data file, and reviewer approval.
Traceability Record
The verification matrix should map each requirement to one test method, one raw evidence file and one reviewer decision. Ambiguous evidence names such as “ECG test passed” should be replaced by stable identifiers: protocol number, data file, firmware hash, calibration certificate and nonconformance record when applicable.
If one test supports several requirements, the report should still state which measured result satisfies each requirement. This prevents a clean waveform from being overused as evidence for leakage current, timestamp integrity or risk-control effectiveness.
Risk-Control Links
Important failure modes include:
- loose electrode or high skin-electrode impedance;
- amplifier saturation from motion or electrode offset;
- mains interference under impedance imbalance;
- aliasing because filtering or sampling configuration is wrong;
- excessive leakage current with the accessory set;
- timestamp discontinuity or data packet loss;
- algorithm output displayed after stale signal quality;
- firmware change that alters filtering without renewed verification.
The project should link each failure mode to a design control, verification test, and residual-risk decision. A clean waveform in one bench condition is not enough evidence for release.
Hold Criteria
Place the acquisition subsystem on hold if any of the following occur:
- unexplained saturation or clipping during the verification waveform;
- mains residual above limit under electrode imbalance;
- leakage-current evidence missing for the released accessory set;
- timestamp regression, sample counter discontinuity or silent data loss;
- heart-rate output displayed without a valid signal-quality state;
- undocumented firmware or filter change after the verification run.
The hold can be lifted only by a documented corrective action and repeated affected tests, not by an engineering judgement note alone.
Final Release Gate
The engineering release decision is:
Release the ECG acquisition subsystem for the stated monitoring verification scope only if SNR, ADC resolution, CMRR, leakage-current, latency, data-integrity, lead-off, saturation, and risk-control tests all pass on the documented hardware, firmware, accessories, and filter configuration.
If any test fails, the report should identify whether the corrective action belongs to hardware design, electrode/accessory specification, shielding, firmware filtering, sampling configuration, alarm logic, usability, or risk management.
For a controlled release, the final signature should reference the exact requirement set, test report, risk-control matrix, configuration baseline and open anomalies. A release with open anomalies can be acceptable only if each anomaly has a documented rationale, risk disposition and owner.