Glossary term

Phase Noise

Engineering definition of phase noise covering oscillator stability, SSB phase noise, integrated jitter, EVM, carrier recovery and validation evidence.

Branch: Telecommunications Engineering
Glossary type: metric
Content: Glossary term
Updated: Jun 26, 2026
Revision: v1.0.0 · reviewed

Definition

metric

Phase noise is the short-term random fluctuation of an oscillator or clock phase, usually specified as noise power density at frequency offsets from a carrier.

Phase noise describes how an oscillator, synthesizer, recovered carrier or sampling clock departs from an ideal single-frequency phase reference. In RF and digital systems it can broaden spectra, degrade EVM, stress carrier recovery, increase sampling jitter, reduce radar coherence and close modulation margin. It is related to timing jitter but is normally specified in the frequency domain as single-sideband phase noise in dBc/Hz at offset frequencies.

Phase noise is the short-term instability of an oscillator, clock or carrier phase. An ideal sinusoid would have all its energy at one frequency. A real oscillator spreads some energy around the carrier because its phase wanders over time. In a communication receiver, that wandering can rotate constellation points. In a transmitter, it can broaden the spectrum. In a sampling system, it can appear as aperture jitter.

The important engineering point is that phase noise is not just a small oscillator data-sheet detail. It can be the limiting impairment when received power, thermal SNR and link margin look acceptable.

Signal Model

A practical carrier can be written as:

v(t)=A\cos(2\pi f_0t+\phi(t))

where:

A is amplitude;
f_0 is nominal carrier or clock frequency;
phi(t) is time-varying phase error.

If phi(t) were constant, it would be a static phase offset. Phase noise refers to random or short-term variation in phi(t).

SSB Phase Noise

Single-sideband phase noise is commonly written:

L(f_m)

where f_m is offset from the carrier. It is usually reported in dBc/Hz, meaning noise power in a 1 Hz bandwidth at the offset, relative to carrier power.

Lower values are better. For example, -110 dBc/Hz at 100 kHz offset is cleaner than -90 dBc/Hz at 100 kHz offset, if measured under comparable conditions.

Integrated Phase Noise And Jitter

For small phase noise, integrated RMS phase error can be estimated from the single-sideband phase-noise curve:

\sigma_\phi^2\approx2\int_{f_1}^{f_2}10^{L(f)/10}\,df

where L(f) is converted from dBc/Hz to linear ratio. The factor of 2 accounts for the single-sideband convention in this common engineering approximation.

The RMS time jitter equivalent is:

\displaystyle \sigma_t=\frac{\sigma_\phi}{2\pi f_0}

The integration limits matter. A data sheet number without integration bandwidth can be misleading because close-in and far-out phase noise affect different systems differently.

Worked Example

A clock at:

f_0=2.4\ \text{GHz}

has integrated phase noise over the relevant receiver loop bandwidth:

\sigma_\phi=0.035\ \text{rad RMS}

Convert this to degrees:

\displaystyle \sigma_{\phi,deg}=0.035\frac{180}{\pi}=2.0^\circ

The equivalent RMS time jitter is:

\displaystyle \sigma_t=\frac{0.035}{2\pi(2.4\times10^9)}

\sigma_t=2.32\ \text{ps RMS}

If the modulation release budget allows:

\sigma_{\phi,allow}=4.0^\circ

then phase-noise margin is:

M_\phi=4.0-2.0=2.0^\circ

The phase reference is acceptable for this simplified phase budget, but only if the integration bandwidth and operating mode match the receiver test.

Relation To EVM

For small random phase error, the RMS EVM contribution can be approximated by:

EVM_\phi\approx\sigma_\phi

where sigma_phi is in radians. In the worked example:

EVM_\phi\approx0.035=3.5\%

This is only one component of EVM. Thermal noise, IQ imbalance, nonlinear distortion, quantization, timing error, equalization error and interference may also contribute.

Engineering Use

Phase noise is used when selecting oscillators, PLLs, synthesizers, clock trees, ADC clocks, local oscillators, radar references and recovered-carrier loops. It affects high-order QAM, OFDM subcarrier orthogonality, radar Doppler resolution, coherent integration, sampling SNR and spectral-mask shoulders.

Mitigation may involve a lower-noise reference, PLL bandwidth change, cleaner power supply, better layout isolation, oscillator replacement, reduced multiplication factor, improved shielding, lower-vibration mounting or a modulation mode with more phase tolerance.

Difference From Jitter

Jitter describes timing variation in the time domain. Phase noise describes phase instability in the frequency domain. They are related through integration and carrier frequency, but they are not interchangeable unless the integration range, reference frequency and measurement method are stated.

In a digital receiver, phase noise can appear as constellation rotation or EVM. In a high-speed ADC, the same clock instability can appear as aperture jitter and reduce SNR for high-frequency inputs.

Validation Evidence

A defensible phase-noise review includes carrier or clock frequency, offset-frequency plot, integration limits, loop bandwidth, PLL configuration, reference source, power-supply condition, temperature, vibration state, multiplication or division factors, measurement instrument noise floor, calibration state and whether the result is free-running, locked, conducted or installed.

Receiver validation should connect the phase-noise number to EVM, carrier-lock behavior, packet error, spectral mask, sampling jitter or radar coherence rather than quoting the oscillator plot alone.

Common Mistakes

Common mistakes include quoting phase noise at one offset as if it described all behavior, converting phase noise to jitter without integration limits, ignoring PLL loop bandwidth, using a bench reference that is cleaner than the installed clock, treating phase noise as thermal noise, and selecting a high-order modulation mode from SNR alone.

The practical rule is to specify the offset curve, integrate over the bandwidth that matters to the receiver or sampler, then compare the resulting phase or time jitter with the actual decision margin.

REF

Disciplines