Glossary term
Zero-Order Hold
A sample-and-hold model that keeps each sampled value constant until the next sampling instant.
Definition
modelA zero-order hold is a sampled-data model or circuit behaviour in which each sample value is held constant until the next sample is available.
Zero-order hold behaviour appears in digital-to-analog conversion, sampled control, discrete simulation, embedded control outputs, and reconstruction of piecewise-constant signals. It introduces delay-like phase lag and frequency-domain shaping that must be considered when continuous plants are controlled by digital algorithms.
A zero-order hold keeps the most recent sampled value constant until a new sample arrives. The output is therefore a staircase signal rather than a continuously varying waveform. This is the natural model for many digital-to-analog converters, pulse-width-modulated control abstractions, and sampled controllers driving continuous plants.
In continuous-time analysis, the ideal zero-order hold has a transfer function:
where T_s is the sampling period. The hold changes both magnitude and phase, so it cannot always be ignored in control-loop design.
Engineering use
Zero-order hold models are used when converting continuous-time plant models to discrete controllers, simulating embedded control loops, designing digital filters, analysing actuator commands, and interpreting sampled data. In digital control, the hold contributes delay-like phase lag that can reduce stability margin, especially when the sampling period is not small compared with plant dynamics.
Real implementations also include computation delay, quantization, actuator bandwidth, saturation, jitter, and update scheduling. A discrete model that includes the hold but ignores these effects may still overpredict performance.
Common mistakes
A common mistake is assuming that a sampled command is equivalent to a continuous command between samples. The actuator sees a held value, and the plant responds to that piecewise-constant input. Another mistake is choosing a sampling rate from the sampling theorem alone while ignoring control bandwidth, phase margin, computation delay, and noise. A strong sampled-control review states sampling period, hold model, computation delay, anti-alias filtering, quantization, actuator dynamics, and validation against continuous-time behaviour.